From: David Miller <davem@davemloft.net>
To: ogerlitz@mellanox.com
Cc: netdev@vger.kernel.org, amirv@mellanox.com, idos@mellanox.com
Subject: Re: [PATCH net-next 0/3] mlx4: CQE/EQE stride support
Date: Fri, 19 Sep 2014 17:32:08 -0400 (EDT) [thread overview]
Message-ID: <20140919.173208.77064865716362179.davem@davemloft.net> (raw)
In-Reply-To: <1411030261-12145-1-git-send-email-ogerlitz@mellanox.com>
From: Or Gerlitz <ogerlitz@mellanox.com>
Date: Thu, 18 Sep 2014 11:50:58 +0300
> This series from Ido Shamay is intended for archs having
> cache line larger then 64 bytes.
>
> Since our CQE/EQEs are generally 64B in those systems, HW will write
> twice to the same cache line consecutively, causing pipe locks due to
> he hazard prevention mechanism. For elements in a cyclic buffer, writes
> are consecutive, so entries smaller than a cache line should be
> avoided, especially if they are written at a high rate.
>
> Reduce consecutive writes to same cache line in CQs/EQs, by allowing the
> driver to increase the distance between entries so that each will reside
> in a different cache line.
Series applied, thanks.
prev parent reply other threads:[~2014-09-19 21:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-18 8:50 [PATCH net-next 0/3] mlx4: CQE/EQE stride support Or Gerlitz
2014-09-18 8:50 ` [PATCH net-next 1/3] net/mlx4_core: Enable " Or Gerlitz
2014-09-18 8:51 ` [PATCH net-next 2/3] net/mlx4_core: Cache line EQE size support Or Gerlitz
2014-09-18 8:51 ` [PATCH net-next 3/3] net/mlx4_en: Add mlx4_en_get_cqe helper Or Gerlitz
2014-09-19 21:32 ` David Miller [this message]
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