From: Andrew Lunn <andrew@lunn.ch>
To: Mathieu Olivari <mathieu@codeaurora.org>
Cc: netdev@vger.kernel.org, linux@roeck-us.net, jogo@openwrt.org,
f.fainelli@gmail.com
Subject: Re: RFC: dsa: add support for multiple CPU ports
Date: Tue, 10 Mar 2015 22:13:15 +0100 [thread overview]
Message-ID: <20150310211315.GF10838@lunn.ch> (raw)
In-Reply-To: <20150310204021.GA2740@codeaurora.org>
> I was thinking about the MIB counters, maintained by the switch, on the CPU
> port(s).
>
> On this picture:
>
> +-----------+ +--------------------+
> | | RGMII | |
> | eth0+-------+ P0 P1 +------ 1000baseT MDI ("WAN")
> | wan| | 7-port P2 +------ 1000baseT MDI ("LAN1")
> | CPU | | ethernet P3 +------ 1000baseT MDI ("LAN2")
> | | RGMII | switch P4 +------ 1000baseT MDI ("LAN3")
> | eth1+-------+ P6 w/5 PHYs P5 +------ 1000baseT MDI ("LAN4")
> | lan| | |
> +-----------+ +--------------------+
> | MDIO |
> \------------/
>
> We can see MIB stats of P1/P2/P3/P4/P5 by using ethtool -S. But as CPU
> ports don't have a net_device, there isn't a way to access MIB stats of
> P0 & P6.
Ah, sorry, i misunderstood you. As you say, the current DSA does not
give you access to these counters. Apart from these counters, are
there any other needs to have access to these ports? The core idea of
hardware acceleration is that it should look like linux as normal. P0
and P6 are an internal detail, and you cannot actually use them. You
cannot send packets, they are something special. So unless there is a
good reason, we should not expose them.
> If we have the eth0 <--> P0 and eth1 <--> P6 relationship information in dts,
> we could use it to lookup which switch port is connected to this net_dev and
> show the corresponding counters when running "ethtool -S ethN".
But that is not what the user expects. They expect the statistic
counters for ethN, not the switch port.
Andrew
next prev parent reply other threads:[~2015-03-10 21:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-10 19:01 RFC: dsa: add support for multiple CPU ports Mathieu Olivari
2015-03-10 19:21 ` Andrew Lunn
2015-03-10 22:13 ` Mathieu Olivari
2015-03-10 22:50 ` Andrew Lunn
2015-03-10 19:31 ` Andrew Lunn
2015-03-10 20:42 ` Mathieu Olivari
2015-03-10 21:13 ` Andrew Lunn [this message]
2015-03-10 22:53 ` Mathieu Olivari
2015-03-11 1:47 ` David Miller
2015-03-11 13:07 ` Jiri Pirko
2015-03-11 0:01 ` Florian Fainelli
2015-03-11 1:18 ` Mathieu Olivari
2015-03-11 13:30 ` Andrew Lunn
2015-03-11 23:37 ` Mathieu Olivari
2015-03-12 0:19 ` Andrew Lunn
2015-03-13 1:57 ` Mathieu Olivari
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