From: Guenter <linux@roeck-us.net>
To: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Cc: netdev <netdev@vger.kernel.org>,
Florian Fainelli <f.fainelli@gmail.com>,
David <davem@davemloft.net>, Andrew Lunn <andrew@lunn.ch>,
linux-kernel <linux-kernel@vger.kernel.org>,
kernel <kernel@savoirfairelinux.com>
Subject: Re: [PATCH 1/2] net: dsa: mv88e6xxx: sleep in _mv88e6xxx_stats_wait
Date: Fri, 10 Jul 2015 13:05:15 -0700 [thread overview]
Message-ID: <20150710200514.GA9469@groeck-UX31A> (raw)
In-Reply-To: <645518234.216003.1436556107630.JavaMail.zimbra@savoirfairelinux.com>
Hi Vivien,
On Fri, Jul 10, 2015 at 03:21:47PM -0400, Vivien Didelot wrote:
> Hi Guenter,
> >> I must have missed where is the benefit from spin reading 10 times this
> >> register, rather than sleeping 1ms between tests. Does this busy bit
> >> behaves differently from the phy, atu, scratch, or vtu busy bits?
> >>
> > Benefit is reaction time, mostly. If the result isn't ready after the
> > first spin, the new code path adds a mandatory 1-2ms delay. This could
> > add up to a lot if that kind of retry is seen a lot.
>
> To me, it looks like if this mandatory 1-2ms delay is an issue, then
> _mv88e6xxx_wait must be fixed. Maybe reducing this delay is an option?
>
Good point. The timeout is most definitely quite large and for sure on
the safe side. It might make sense to add some statistics gathering to
see how long the maximum observed delay actually is.
Guenter
next prev parent reply other threads:[~2015-07-10 20:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-10 16:57 [PATCH 1/2] net: dsa: mv88e6xxx: sleep in _mv88e6xxx_stats_wait Vivien Didelot
2015-07-10 16:57 ` [PATCH 2/2] net: dsa: mv88e6xxx: call _mv88e6xxx_stats_wait with SMI lock held Vivien Didelot
2015-07-10 17:13 ` Guenter
2015-07-10 17:10 ` [PATCH 1/2] net: dsa: mv88e6xxx: sleep in _mv88e6xxx_stats_wait Guenter
2015-07-10 18:20 ` Vivien Didelot
2015-07-10 18:36 ` Guenter Roeck
2015-07-10 19:21 ` Vivien Didelot
2015-07-10 20:05 ` Guenter [this message]
2015-07-18 14:58 ` Andrew Lunn
2015-07-18 15:23 ` Vivien Didelot
2015-07-18 15:28 ` Andrew Lunn
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