[PATCH 00/28] MIPS Boston board support

[PATCH 00/28] MIPS Boston board support

[Paul Burton]

This series introduces support for the Imagination Technologies MIPS
Boston development board. Boston is an FPGA-based development board
akin to the much older Malta board, built around a Xilinx FPGA running
a MIPS CPU & other logic including a PCIe root port connected to an
Intel EG20T Platform Controller Hub. This provides a base set of
peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
slots are also present for expansion.

Paul Burton (28):
  serial: earlycon: allow MEM32 I/O for DT earlycon
  dt-bindings: ascii-lcd: Document a binding for simple ASCII LCDs
  auxdisplay: driver for simple memory mapped ASCII LCD displays
  MIPS: PCI: compatibility with ARM-like PCI host drivers
  PCI: xilinx: keep references to both IRQ domains
  PCI: xilinx: unify INTx & MSI interrupt FIFO decode
  PCI: xilinx: always clear interrupt decode register
  PCI: xilinx: fix INTX irq dispatch
  PCI: xilinx: allow build on MIPS platforms
  misc: pch_phub: allow build on MIPS platforms
  dmaengine: pch_dma: allow build on MIPS platforms
  gpio: pch: allow build on MIPS platforms
  gpio: pch: allow use from device tree
  i2c: eg20t: allow build on MIPS platforms
  i2c: eg20t: set i2c_adapter->dev.of_node
  rtc: m41t80: add devicetree probe support
  spi: topcliff-pch: allow build for MIPS platforms
  ptp: pch: allow build on MIPS platforms
  net: pch_gbe: allow build on MIPS platforms
  net: pch_gbe: clear interrupt FIFO during probe
  net: pch_gbe: mark Minnow PHY reset GPIO active low
  net: pch_gbe: pull PHY GPIO handling out of Minnow code
  net: pch_gbe: always reset PHY along with MAC
  net: pch_gbe: add device tree support
  net: pch_gbe: allow longer for resets
  MIPS: support for generating FIT (.itb) images
  dt-bindings: mips: img,boston: Document img,boston binding
  MIPS: Boston board support

 Documentation/devicetree/bindings/ascii-lcd.txt    |  10 +
 .../devicetree/bindings/mips/img/boston.txt        |  15 ++
 MAINTAINERS                                        |  14 ++
 arch/mips/Kbuild.platforms                         |   1 +
 arch/mips/Kconfig                                  |  45 ++++
 arch/mips/Makefile                                 |   6 +-
 arch/mips/boot/Makefile                            |  61 ++++++
 arch/mips/boot/dts/Makefile                        |   1 +
 arch/mips/boot/dts/img/Makefile                    |   7 +
 arch/mips/boot/dts/img/boston.dts                  | 201 ++++++++++++++++++
 arch/mips/boot/skeleton.its                        |  24 +++
 arch/mips/boston/Makefile                          |  12 ++
 arch/mips/boston/Platform                          |   8 +
 arch/mips/boston/init.c                            |  75 +++++++
 arch/mips/boston/int.c                             |  33 +++
 arch/mips/boston/time.c                            |  89 ++++++++
 arch/mips/boston/vmlinux.its                       |  23 ++
 arch/mips/configs/boston_defconfig                 | 170 +++++++++++++++
 .../asm/mach-boston/cpu-feature-overrides.h        |  26 +++
 arch/mips/include/asm/mach-boston/irq.h            |  18 ++
 arch/mips/include/asm/mach-boston/spaces.h         |  20 ++
 arch/mips/include/asm/pci.h                        |  67 +++++-
 arch/mips/lib/iomap-pci.c                          |   2 +-
 arch/mips/pci/Makefile                             |   6 +
 arch/mips/pci/pci-generic.c                        | 138 ++++++++++++
 arch/mips/pci/pci-legacy.c                         | 232 +++++++++++++++++++++
 arch/mips/pci/pci.c                                | 226 +-------------------
 drivers/auxdisplay/Kconfig                         |   7 +
 drivers/auxdisplay/Makefile                        |   1 +
 drivers/auxdisplay/ascii-lcd.c                     | 230 ++++++++++++++++++++
 drivers/dma/Kconfig                                |   2 +-
 drivers/gpio/Kconfig                               |   2 +-
 drivers/gpio/gpio-pch.c                            |   1 +
 drivers/i2c/busses/Kconfig                         |   2 +-
 drivers/i2c/busses/i2c-eg20t.c                     |   1 +
 drivers/misc/Kconfig                               |   2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig      |   2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h    |   4 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   |  74 +++++--
 drivers/of/fdt.c                                   |   2 +-
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pcie-xilinx.c                     | 123 +++++------
 drivers/ptp/Kconfig                                |   2 +-
 drivers/rtc/rtc-m41t80.c                           |  26 +++
 drivers/spi/Kconfig                                |   2 +-
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/earlycon.c                      |  15 +-
 include/linux/serial_core.h                        |   2 +-
 48 files changed, 1720 insertions(+), 313 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ascii-lcd.txt
 create mode 100644 Documentation/devicetree/bindings/mips/img/boston.txt
 create mode 100644 arch/mips/boot/dts/img/Makefile
 create mode 100644 arch/mips/boot/dts/img/boston.dts
 create mode 100644 arch/mips/boot/skeleton.its
 create mode 100644 arch/mips/boston/Makefile
 create mode 100644 arch/mips/boston/Platform
 create mode 100644 arch/mips/boston/init.c
 create mode 100644 arch/mips/boston/int.c
 create mode 100644 arch/mips/boston/time.c
 create mode 100644 arch/mips/boston/vmlinux.its
 create mode 100644 arch/mips/configs/boston_defconfig
 create mode 100644 arch/mips/include/asm/mach-boston/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-boston/irq.h
 create mode 100644 arch/mips/include/asm/mach-boston/spaces.h
 create mode 100644 arch/mips/pci/pci-generic.c
 create mode 100644 arch/mips/pci/pci-legacy.c
 create mode 100644 drivers/auxdisplay/ascii-lcd.c

-- 
2.6.2

[PATCH 18/28] ptp: pch: allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index ee3de34..ee43549 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -74,7 +74,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
 	tristate "Intel PCH EG20T as PTP clock"
-	depends on X86_32 || COMPILE_TEST
+	depends on X86_32 || MIPS || COMPILE_TEST
 	depends on HAS_IOMEM && NET
 	select PTP_1588_CLOCK
 	help
-- 
2.6.2

[PATCH 19/28] net: pch_gbe: allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a352..4d3809a 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
 	tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	select MII
 	select PTP_1588_CLOCK_PCH
 	select NET_PTP_CLASSIFY
-- 
2.6.2

[PATCH 21/28] net: pch_gbe: mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 3b98b263b..fde4c11 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2717,7 +2717,8 @@ err_free_netdev:
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+		GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
 	unsigned gpio = MINNOW_PHY_RESET_GPIO;
 	int ret;
 
@@ -2729,10 +2730,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 		return ret;
 	}
 
-	gpio_set_value(gpio, 0);
-	usleep_range(1250, 1500);
 	gpio_set_value(gpio, 1);
 	usleep_range(1250, 1500);
+	gpio_set_value(gpio, 0);
+	usleep_range(1250, 1500);
 
 	return ret;
 }
-- 
2.6.2

[PATCH 22/28] net: pch_gbe: pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h    |  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++-------
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 2a55d6d..884f90b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -582,15 +582,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:		PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:		Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate:	Bool, disable PHY hibernation
  * @platform_init:		Platform initialization callback, called from
  *				probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+	struct gpio_desc *phy_reset_gpio;
 	bool phy_tx_clk_delay;
 	bool phy_disable_hibernate;
-	int (*platform_init)(struct pci_dev *pdev);
+	int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index fde4c11..23d28f0 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 	pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+	struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+	if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+		return;
+
+	gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:	Pointer to the HW structure
@@ -2627,7 +2637,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 	adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
 	adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
 	if (adapter->pdata && adapter->pdata->platform_init)
-		adapter->pdata->platform_init(pdev);
+		adapter->pdata->platform_init(pdev, pdata);
+
+	if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+		pch_gbe_phy_set_reset(&adapter->hw, 1);
+		usleep_range(1250, 1500);
+		pch_gbe_phy_set_reset(&adapter->hw, 0);
+		usleep_range(1250, 1500);
+	}
 
 	adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
 					       PCI_DEVFN(12, 4));
@@ -2715,7 +2732,8 @@ err_free_netdev:
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+					struct pch_gbe_privdata *pdata)
 {
 	unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
 		GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2724,16 +2742,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 
 	ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
 				    "minnow_phy_reset");
-	if (ret) {
+	if (!ret)
+		pdata->phy_reset_gpio = gpio_to_desc(gpio);
+	else
 		dev_err(&pdev->dev,
 			"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-		return ret;
-	}
-
-	gpio_set_value(gpio, 1);
-	usleep_range(1250, 1500);
-	gpio_set_value(gpio, 0);
-	usleep_range(1250, 1500);
 
 	return ret;
 }
-- 
2.6.2

[PATCH 23/28] net: pch_gbe: always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 23d28f0..824ff9e 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -378,10 +378,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
 	/* Read the MAC address. and store to the private data */
 	pch_gbe_mac_read_mac_addr(hw);
+	pch_gbe_phy_set_reset(hw, 1);
 	iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
 	iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 #endif
+	pch_gbe_phy_set_reset(hw, 0);
+	usleep_range(1250, 1500);
 	pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 	/* Setup the receive addresses */
 	pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.6.2

[PATCH 24/28] net: pch_gbe: add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 824ff9e..f2a9a38 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include <linux/net_tstamp.h>
 #include <linux/ptp_classify.h>
 #include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_gpio.h>
 
 #define DRV_VERSION     "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2594,13 +2596,41 @@ static void pch_gbe_remove(struct pci_dev *pdev)
 	free_netdev(netdev);
 }
 
+static int pch_gbe_parse_dt(struct pci_dev *pdev,
+			    struct pch_gbe_privdata **pdata)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct gpio_desc *gpio;
+
+	if (!config_enabled(CONFIG_OF) || !np)
+		return 0;
+
+	if (!*pdata)
+		*pdata = devm_kzalloc(&pdev->dev, sizeof(**pdata), GFP_KERNEL);
+	if (!*pdata)
+		return -ENOMEM;
+
+	gpio = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_ASIS);
+	if (IS_ERR(gpio))
+		return PTR_ERR(gpio);
+
+	(*pdata)->phy_reset_gpio = gpio;
+	return 0;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *pci_id)
 {
 	struct net_device *netdev;
 	struct pch_gbe_adapter *adapter;
+	struct pch_gbe_privdata *pdata;
 	int ret;
 
+	pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+	ret = pch_gbe_parse_dt(pdev, &pdata);
+	if (ret)
+		goto err_out;
+
 	ret = pcim_enable_device(pdev);
 	if (ret)
 		return ret;
@@ -2638,7 +2668,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 	adapter->pdev = pdev;
 	adapter->hw.back = adapter;
 	adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-	adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+	adapter->pdata = pdata;
 	if (adapter->pdata && adapter->pdata->platform_init)
 		adapter->pdata->platform_init(pdev, pdata);
 
@@ -2729,6 +2759,7 @@ err_free_adapter:
 	pch_gbe_hal_phy_hw_reset(&adapter->hw);
 err_free_netdev:
 	free_netdev(netdev);
+err_out:
 	return ret;
 }
 
-- 
2.6.2

[PATCH 25/28] net: pch_gbe: allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Bump up
the number of loops.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index f2a9a38..f650f45 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -321,7 +321,7 @@ static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 	u32 tmp;
 
 	/* wait busy */
-	tmp = 1000;
+	tmp = 10000;
 	while ((ioread32(reg) & bit) && --tmp)
 		cpu_relax();
 	if (!tmp)
-- 
2.6.2

Re: [PATCH 00/28] MIPS Boston board support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 879 bytes --]

On Mon, Nov 30, 2015 at 04:21:25PM +0000, Paul Burton wrote:
> This series introduces support for the Imagination Technologies MIPS
> Boston development board. Boston is an FPGA-based development board
> akin to the much older Malta board, built around a Xilinx FPGA running
> a MIPS CPU & other logic including a PCIe root port connected to an
> Intel EG20T Platform Controller Hub. This provides a base set of
> peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
> slots are also present for expansion.

This is an insanely big CC list :(

What are the interdependencies here - does this really need to be one
patch series or can the individual driver changes go in separately?  The
latter is more normal, usually rather than a single patch series we just
have each driver sent by itself since that's usually easier to handle
and avoids the massive CC lists.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

Re: [PATCH 18/28] ptp: pch: allow build on MIPS platforms

[Richard Cochran]

On Mon, Nov 30, 2015 at 04:21:43PM +0000, Paul Burton wrote:
> Allow the ptp_pch driver to be built on MIPS platforms in preparation
> for use on the MIPS Boston board.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Acked-by: Richard Cochran <richardcochran@gmail.com>

Re: [PATCH 00/28] MIPS Boston board support

[Linus Walleij]

On Mon, Nov 30, 2015 at 5:34 PM, Mark Brown <broonie@kernel.org> wrote:
> On Mon, Nov 30, 2015 at 04:21:25PM +0000, Paul Burton wrote:
>> This series introduces support for the Imagination Technologies MIPS
>> Boston development board. Boston is an FPGA-based development board
>> akin to the much older Malta board, built around a Xilinx FPGA running
>> a MIPS CPU & other logic including a PCIe root port connected to an
>> Intel EG20T Platform Controller Hub. This provides a base set of
>> peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
>> slots are also present for expansion.
>
> This is an insanely big CC list :(
>
> What are the interdependencies here - does this really need to be one
> patch series or can the individual driver changes go in separately?

I took the two GPIO patches and ran off with them at least.

Yours,
Linus Walleij

Re: [PATCH 24/28] net: pch_gbe: add device tree support

[Andy Shevchenko]

On Mon, Nov 30, 2015 at 6:21 PM, Paul Burton <paul.burton@imgtec.com> wrote:
> Introduce support for retrieving the PHY reset GPIO from device tree,
> which will be used on the MIPS Boston development board. This requires
> support for probe deferral in order to work correctly, since the order
> of device probe is not guaranteed & typically the EG20T GPIO controller
> device will be probed after the ethernet MAC.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> index 824ff9e..f2a9a38 100644
> --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> @@ -23,6 +23,8 @@
>  #include <linux/net_tstamp.h>
>  #include <linux/ptp_classify.h>
>  #include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/of_gpio.h>
>
>  #define DRV_VERSION     "1.01"
>  const char pch_driver_version[] = DRV_VERSION;
> @@ -2594,13 +2596,41 @@ static void pch_gbe_remove(struct pci_dev *pdev)
>         free_netdev(netdev);
>  }
>
> +static int pch_gbe_parse_dt(struct pci_dev *pdev,
> +                           struct pch_gbe_privdata **pdata)

Why not to return pdata as it done in many other drivers?
You have ERR_PTR() macro to pass errors.

> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct gpio_desc *gpio;
> +
> +       if (!config_enabled(CONFIG_OF) || !np)

Before I saw IS_ENABLED(). Is this one a preferable new API?

> +               return 0;
> +
> +       if (!*pdata)
> +               *pdata = devm_kzalloc(&pdev->dev, sizeof(**pdata), GFP_KERNEL);
> +       if (!*pdata)
> +               return -ENOMEM;
> +
> +       gpio = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_ASIS);
> +       if (IS_ERR(gpio))
> +               return PTR_ERR(gpio);
> +
> +       (*pdata)->phy_reset_gpio = gpio;
> +       return 0;
> +}
> +
>  static int pch_gbe_probe(struct pci_dev *pdev,
>                           const struct pci_device_id *pci_id)
>  {
>         struct net_device *netdev;
>         struct pch_gbe_adapter *adapter;
> +       struct pch_gbe_privdata *pdata;
>         int ret;
>
> +       pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
> +       ret = pch_gbe_parse_dt(pdev, &pdata);

So, I didn;t see anything related to dt in that function.
Maybe you just call it always? In that case remove check for np.

> +       if (ret)
> +               goto err_out;
> +
>         ret = pcim_enable_device(pdev);
>         if (ret)
>                 return ret;
> @@ -2638,7 +2668,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
>         adapter->pdev = pdev;
>         adapter->hw.back = adapter;
>         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
> -       adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
> +       adapter->pdata = pdata;
>         if (adapter->pdata && adapter->pdata->platform_init)
>                 adapter->pdata->platform_init(pdev, pdata);
>
> @@ -2729,6 +2759,7 @@ err_free_adapter:
>         pch_gbe_hal_phy_hw_reset(&adapter->hw);
>  err_free_netdev:
>         free_netdev(netdev);
> +err_out:

Redundant.

>         return ret;
>  }

For now it's a common practice to mix styles in probe due to usage of
devres API.

-- 
With Best Regards,
Andy Shevchenko