From: David Miller <davem@davemloft.net>
To: jszhang@marvell.com
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
Date: Thu, 31 Mar 2016 15:15:42 -0400 (EDT) [thread overview]
Message-ID: <20160331.151542.1145855002785328972.davem@davemloft.net> (raw)
In-Reply-To: <1459338821-343-1-git-send-email-jszhang@marvell.com>
From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 30 Mar 2016 19:53:41 +0800
> The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline
> size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES.
>
> And since dma_alloc_coherent() is always cacheline size aligned, so
> remove the align checks.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Applied.
prev parent reply other threads:[~2016-03-31 19:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 11:53 [PATCH] net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Jisheng Zhang
2016-03-31 19:15 ` David Miller [this message]
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