From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Miller <davem@davemloft.net>
Subject: Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with
 L1_CACHE_BYTES
Date: Thu, 31 Mar 2016 16:47:10 -0400 (EDT)
Message-ID: <20160331.164710.1998871529914699937.davem@davemloft.net>
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	<20160331223735.32904e42@free-electrons.com>
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Cc: jszhang@marvell.com, netdev@vger.kernel.org,
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To: thomas.petazzoni@free-electrons.com
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Thu, 31 Mar 2016 22:37:35 +0200

> Hello,
> 
> On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote:
>> From: Jisheng Zhang <jszhang@marvell.com>
>> Date: Wed, 30 Mar 2016 19:55:21 +0800
>> 
>> > The mvneta is also used in some Marvell berlin family SoCs which may
>> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
>> > usage with L1_CACHE_BYTES.
>> > 
>> > And since dma_alloc_coherent() is always cacheline size aligned, so
>> > remove the align checks.
>> > 
>> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
>> 
>> Applied.
> 
> A new version of the patch was sent, which more rightfully uses
> cache_line_size(), see:
> 
>  "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size"

Sorry about that.

Send me a realtive fixup patch if you like.

Thanks.