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From: Andrew Lunn <andrew@lunn.ch>
To: Timur Tabi <timur@codeaurora.org>
Cc: netdev@vger.kernel.org
Subject: Re: Need help with mdiobus_register and phy
Date: Fri, 14 Oct 2016 19:25:14 +0200	[thread overview]
Message-ID: <20161014172514.GA23455@lunn.ch> (raw)
In-Reply-To: <58010E79.2030607@codeaurora.org>

On Fri, Oct 14, 2016 at 11:57:29AM -0500, Timur Tabi wrote:
> Andrew Lunn wrote:
> >That is a basic assumption of the code. If you cannot read the IDs how
> >are you supposed to know what device it is, and what quirks you need
> >to work around its broken features...
> >
> >Does the datasheet say anything about this?
> >
> >I would say for this device, suspend() is too aggressive.
> 
> This change in my driver makes the problem go away (I'm not sure if
> it's a "fix"):
> 
> @@ -992,7 +992,7 @@ int emac_mac_up(struct emac_adapter *adpt)
>         emac_mac_rx_descs_refill(adpt, &adpt->rx_q);
> 
>         ret = phy_connect_direct(netdev, adpt->phydev, emac_adjust_link,
> -                                PHY_INTERFACE_MODE_SGMII);
> +                                PHY_INTERFACE_MODE_NA);

It is normal to get the phy-mode from device tree. I've no idea what
ACPI is supposed to do. Setting it to PHY_INTERFACE_MODE_NA means you
assume the boot loader has correctly setup the hardware. You ACPI
firmware might of done this, but there is no guarantee a device tree
base bootloader has. So i would prefer not changing this.
 
> With the interface not set as SGMII, the following code in
> at803x_suspend() is not executed:
> 
> /* also power-down SGMII interface */
> ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
> phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
> phy_write(phydev, MII_BMCR, phy_read(phydev, MII_BMCR) | BMCR_PDOWN);
> phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
> 
> I don't see any other driver issue BMCR_PDOWN in their functions.  I
> added some printks for the PHYSID1 and PHYSID2 registers before and
> after BMCR_PDOWN:
> 
> at803x_suspend:235 MII_PHYSID1=004d MII_PHYSID2=d074
> at803x_suspend:242 MII_PHYSID1=ffff MII_PHYSID2=ffff
> 
> So after calling BMCR_PDOWN, the PHYSID1 and PHYSID2 registers are
> no longer readable.  Is that expected?

You are making two changes here. Is it the SGMII power down which is
causing the id registers to return 0xffff, or the BMCR_PDOWN.

The generic suspend code sets the PDOWN bit, so it is assuming the PHY
will respond afterwards.

     Andrew

  reply	other threads:[~2016-10-14 17:25 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-13 23:15 Need help with mdiobus_register and phy Timur Tabi
2016-10-14  4:06 ` Andrew Lunn
2016-10-14 11:38   ` Timur Tabi
2016-10-14 12:06     ` Andrew Lunn
2016-10-14 12:39       ` Timur Tabi
2016-10-14 12:49         ` Andrew Lunn
2016-10-14 12:49           ` Timur Tabi
2016-10-14 12:57             ` Andrew Lunn
2016-10-14 13:03               ` Timur Tabi
2016-10-14 13:18                 ` Andrew Lunn
2016-10-14 13:28                   ` Timur Tabi
2016-10-14 16:57                   ` Timur Tabi
2016-10-14 17:25                     ` Andrew Lunn [this message]
2016-10-14 18:30                       ` Timur Tabi
2016-10-15 10:19                       ` Florian Fainelli
2016-10-15 14:39                         ` Timur Tabi
2016-10-15 18:02                           ` Andrew Lunn
2016-10-15 18:28                             ` Timur Tabi
2016-10-17  9:05                               ` Zefir Kurtisi
2016-10-17 20:53                                 ` Timur Tabi
2016-10-18 10:31                                   ` Zefir Kurtisi
2016-10-18 12:40                                     ` Timur Tabi
2016-10-19  8:55                                       ` Zefir Kurtisi
2016-10-19 12:16                                         ` Timur Tabi
2016-10-20 12:55                                           ` Zefir Kurtisi
2016-10-21  7:44                                             ` Zefir Kurtisi
2016-10-21 11:19                                               ` Timur Tabi

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