From: David Miller <davem@davemloft.net>
To: David.Laight@ACULAB.COM
Cc: alexander.duyck@gmail.com, netdev@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: Disabling msix interrupts
Date: Tue, 07 Feb 2017 11:26:45 -0500 (EST) [thread overview]
Message-ID: <20170207.112645.492478528794181275.davem@davemloft.net> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6DB027DA37@AcuExch.aculab.com>
From: David Laight <David.Laight@ACULAB.COM>
Date: Tue, 7 Feb 2017 09:55:47 +0000
> From: David Miller
>> Sent: 06 February 2017 19:15
>> From: David Laight <David.Laight@ACULAB.COM>
>> Date: Mon, 6 Feb 2017 17:23:54 +0000
>>
>> > Although the 'store buffer' on the sparc cpus I used to use would
>> > let reads overtake writes. So you did have to read back the address
>> > of the last write - not sure about modern sparc cpus.
>>
>> Never would any sparc cpu do so when any of the operations involved
>> were to "side effect" locations, as PCI config space is.
>
> I guess they used non-zero ASI, and that forced the flush??
> Normal uncached memory reads would overtake writes.
> (These were SuperSparc (Viking)).
On sun4m it was controlled by bits in the physical address.
prev parent reply other threads:[~2017-02-07 16:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-06 15:33 Disabling msix interrupts David Laight
2017-02-06 16:26 ` Alexander Duyck
2017-02-06 17:23 ` David Laight
2017-02-06 19:14 ` David Miller
2017-02-07 9:55 ` David Laight
2017-02-07 16:26 ` David Miller [this message]
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