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From: David Miller <davem@davemloft.net>
To: ast@fb.com
Cc: daniel@iogearbox.net, netdev@vger.kernel.org, xi.wang@gmail.com,
	catalin.marinas@arm.com
Subject: Re: sparc64 and ARM64 JIT bug
Date: Mon, 01 May 2017 23:19:08 -0400 (EDT)	[thread overview]
Message-ID: <20170501.231908.1478616679170333208.davem@davemloft.net> (raw)
In-Reply-To: <20170501.230234.787989809925411599.davem@davemloft.net>

From: David Miller <davem@davemloft.net>
Date: Mon, 01 May 2017 23:02:34 -0400 (EDT)

> 	for (i = 0; i < prog->len; i++) {
> 		const struct bpf_insn *insn = &prog->insnsi[i];
> 		int ret;
> 
> 		ret = build_insn(insn, ctx);
> 		ctx->offset[i] = ctx->idx;
> 
> 		if (ret > 0) {
> 			i++;
> 			continue;
> 		}
> 		if (ret)
> 			return ret;
> 	}

Ok, the fix is to defer the ctx->offset[i] setting until after the
potential extra "i++" increment inside of the "if (ret > 0)" test.

This is how x86_64's JIT handles this.

I'm testing this fix on sparc64 now.

  reply	other threads:[~2017-05-02  3:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-02  2:31 LLVM 4.0 code generation bug David Miller
2017-05-02  2:39 ` Alexei Starovoitov
2017-05-02  2:41   ` David Miller
2017-05-02  3:02   ` sparc64 and ARM64 JIT bug (was Re: LLVM 4.0 code generation bug) David Miller
2017-05-02  3:19     ` David Miller [this message]
2017-05-02 14:11     ` Daniel Borkmann

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