From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jason Gunthorpe Subject: Re: [for-next 4/6] net/mlx5: FPGA, Add basic support for Innova Date: Wed, 7 Jun 2017 09:48:58 -0600 Message-ID: <20170607154858.GA30124@obsidianresearch.com> References: <20170529160252.GA27550@obsidianresearch.com> <20170601153704.GA1680@obsidianresearch.com> <20170605151724.GA20182@obsidianresearch.com> <20170606161709.GA8671@obsidianresearch.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Ilan Tayari , Alexei Starovoitov , "David S. Miller" , Doug Ledford , "netdev@vger.kernel.org" , "linux-rdma@vger.kernel.org" , "jsorensen@fb.com" , Andy Shevchenko , "linux-fpga@vger.kernel.org" , Alan Tull , "yi1.li@linux.intel.com" , Boris Pismenny To: Saeed Mahameed Return-path: Received: from quartz.orcorp.ca ([184.70.90.242]:43828 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750831AbdFGPtN (ORCPT ); Wed, 7 Jun 2017 11:49:13 -0400 Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org List-ID: On Wed, Jun 07, 2017 at 07:16:42AM +0300, Saeed Mahameed wrote: > On Tue, Jun 6, 2017 at 7:17 PM, Jason Gunthorpe > wrote: > > On Tue, Jun 06, 2017 at 06:52:15AM +0000, Ilan Tayari wrote: > > > >> So neither the host stack nor the network are aware of them. > >> They exist momentarily only on the internal traces on the board and not > >> anywhere else. > > > > Is that really true? If you are creating rocee QPs' then the RDMA > > stack sees this stuff and now we have buried a RDMA ULP inside an > > ethernet driver which seems really wonky.. > > It is not an ethernet driver, mlx5_core provides both RDMA and > ethernet interfaces to both mlx5_ib and the mlx5e netdevice. > > so it is perfectly capable of creating QPs on its own, after all it is > the one creating QPs for the RDMA stack :). > > rdma_create_qp->mlx5_ib_create_qp->mlx5_core_create_qp. Wait, so you built a RDMA ULP inside your driver without using the RDMA API? This keep getting more ugly :( What about security? What if user space sends some raw packets to the FPGA - can it reprogram the ISPEC settings or worse? Jason