From: David Miller <davem@davemloft.net>
To: dingtianhong@huawei.com
Cc: leedom@chelsio.com, ashok.raj@intel.com, bhelgaas@google.com,
helgaas@kernel.org, werner@chelsio.com, ganeshgr@chelsio.com,
asit.k.mallick@intel.com, patrick.j.cramer@intel.com,
Suravee.Suthikulpanit@amd.com, Bob.Shaw@amd.com,
l.stach@pengutronix.de, amira@mellanox.com,
gabriele.paoloni@huawei.com, David.Laight@aculab.com,
jeffrey.t.kirsher@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com, mark.rutland@arm.com, robin.murphy@arm.com,
alexander.duyck@gmail.com, linux-arm-kernel@lists.infradead.org,
netdev@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linuxarm@huawei.com
Subject: Re: [PATCH v10 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Date: Mon, 14 Aug 2017 11:15:31 -0700 (PDT) [thread overview]
Message-ID: <20170814.111531.1800078635180250504.davem@davemloft.net> (raw)
In-Reply-To: <1502725499-11276-1-git-send-email-dingtianhong@huawei.com>
It looks like we are really close on this.
Please just remove the Intel signoff from the AMD patch, and I don't
think it's wise to wait for an AMD person to signoff on it given
the state of affairs for that chipset.
Thanks.
prev parent reply other threads:[~2017-08-14 18:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-14 15:44 [PATCH v10 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong
2017-08-14 15:44 ` [PATCH v10 1/5] PCI: Disable PCIe Relaxed Ordering if unsupported Ding Tianhong
2017-08-14 15:44 ` [PATCH v10 2/5] PCI: Disable Relaxed Ordering for some Intel processors Ding Tianhong
2017-08-14 15:44 ` [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Ding Tianhong
2017-08-14 17:19 ` Raj, Ashok
2017-08-14 18:07 ` Casey Leedom
2017-08-15 1:40 ` Ding Tianhong
2017-08-14 15:44 ` [PATCH v10 4/5] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong
2017-08-14 15:44 ` [PATCH v10 5/5] net/cxgb4vf: " Ding Tianhong
2017-08-14 18:15 ` David Miller [this message]
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