From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH] net: dsa: allow XAUI phy interface mode Date: Fri, 8 Dec 2017 17:26:43 +0100 Message-ID: <20171208162643.GD30846@lunn.ch> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org To: Russell King Return-path: Received: from vps0.lunn.ch ([185.16.172.187]:53584 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753884AbdLHQ0r (ORCPT ); Fri, 8 Dec 2017 11:26:47 -0500 Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org List-ID: On Fri, Dec 08, 2017 at 04:04:59PM +0000, Russell King wrote: > XGMII is a 32-bit bus plus two clock signals per direction. XAUI is > four serial lanes per direction. The 88e6190 supports XAUI but not > XGMII as it doesn't have enough pins. The same is true of 88e6176. > > Match on PHY_INTERFACE_MODE_XAUI for the XAUI port type, but keep > accepting XGMII for backwards compatibility. Hi Russell The backwards compatibility is for the ZII devel C, the DSA link between the two switches? I don't think there are any other boards using this. I will ask around, but i don't think we need to worry about backwards compatibility. There is no region of flash set aside for the DT blob, etc. I always TFTP boot using the one from the kernel, etc. Andrew