Re: [PATCH v5 32/39] dt-bindings: nds32 L2 cache controller Bindings

[Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

On Tue, Jan 02, 2018 at 04:25:04PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> 
> This patch adds nds32 L2 cache controller binding documents.
> 
> Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/nds32/atl2c.txt |   29 +++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt
> new file mode 100644
> index 0000000..db9f7ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
> @@ -0,0 +1,29 @@
> +* Andestech L2 cache Controller
> +
> +The level-2 cache controller plays an important role in reducing memory latency
> +for high performance systems, such as thoese designs with AndesCore processors.
> +Level-2 cache controller in general enhances overall system performance
> +signigicantly and the system power consumption might be reduced as well by
> +reducing DRAM accesses.
> +
> +This binding specifies what properties must be available in the device tree
> +representation of an Andestech L2 cache controller.
> +
> +Required properties:
> +	- compatible:
> +		Usage: required
> +		Value type: <string>
> +		Definition: "andestech,atl2c"
> +	- reg : Physical base address and size of cache controller's memory mapped
> +	- cache-unified : Specifies the cache is a unified cache.
> +	- cache-level : Should be set to 2 for a level 2 cache.
> +
> +* Example
> +
> +	L2: l2-cache@e0500000 {

cache-controller@...

With that,

Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> +		compatible = "andestech,atl2c";
> +		reg = <0xe0500000 0x1000>;
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +
> -- 
> 1.7.9.5
> 
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