From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ivan Mikhaylov Subject: [PATCH v2 2/2] net/ibm/emac: wrong bit is used for STA control register write Date: Tue, 23 Jan 2018 19:48:25 +0300 Message-ID: <20180123164825.48159-1-ivan@de.ibm.com> Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org To: "David S . Miller" , Christian Lamparter , Rob Herring Return-path: Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org STA control register has areas of mode and opcodes for opeations. 18 bit is using for mode selection, where 0 is old MIO/MDIO access method and 1 is indirect access mode. 19-20 bits are using for setting up read/write operation(STA opcodes). In current state 'read' is set into old MIO/MDIO mode with 19 bit and write operation is set into 18 bit which is mode selection, not a write operation. To correlate write with read we set it into 20 bit. All those bit operations are MSB 0 based. Signed-off-by: Ivan Mikhaylov --- drivers/net/ethernet/ibm/emac/emac.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h index d0a0e3b..c26d263 100644 --- a/drivers/net/ethernet/ibm/emac/emac.h +++ b/drivers/net/ethernet/ibm/emac/emac.h @@ -244,7 +244,7 @@ struct emac_regs { #define EMAC_STACR_PHYE 0x00004000 #define EMAC_STACR_STAC_MASK 0x00003000 #define EMAC_STACR_STAC_READ 0x00001000 -#define EMAC_STACR_STAC_WRITE 0x00002000 +#define EMAC_STACR_STAC_WRITE 0x00000800 #define EMAC_STACR_OPBC_MASK 0x00000C00 #define EMAC_STACR_OPBC_50 0x00000000 #define EMAC_STACR_OPBC_66 0x00000400 -- 1.7.1