From mboxrd@z Thu Jan  1 00:00:00 1970
From: Pavel Machek <pavel@ucw.cz>
Subject: Re: [PATCH net-next 2/4] net: stmmac: use correct barrier between
 coherent memory and MMIO
Date: Fri, 2 Mar 2018 10:20:00 +0100
Message-ID: <20180302091959.GC15948@amd>
References: <20180226214709.4359-1-niklas.cassel@axis.com>
 <20180226214709.4359-3-niklas.cassel@axis.com>
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Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Alexandre Torgue <alexandre.torgue@st.com>,
        Jose.Abreu@synopsys.com, Niklas Cassel <niklass@axis.com>,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org
To: Niklas Cassel <niklas.cassel@axis.com>
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Hi!

Thanks for doing the detective work!

> This barrier cannot be a simple dma_wmb(), since a dma_wmb() is only
> used to guarantee the ordering, with respect to other writes,
> to cache coherent DMA memory.

Could you explain this a bit more (and perhaps in code comment)?

Ensuring other writes are done before writing the "GO!" bit should be
enough, no?

(If it is not, do we need heavier barriers in other places, too?)

Best regards,
							Pavel
--=20
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blo=
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