From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-00082601.pphosted.com ([67.231.153.30]:34084 "EHLO mx0b-00082601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752299AbeCUPH5 (ORCPT ); Wed, 21 Mar 2018 11:07:57 -0400 Date: Wed, 21 Mar 2018 08:08:22 -0700 From: Dave Watson To: Saeed Mahameed CC: "David S. Miller" , , Boris Pismenny , Ilya Lesokhin , Aviad Yehezkel Subject: Re: [PATCH net-next 06/14] net/tls: Add generic NIC offload infrastructure Message-ID: <20180321150822.GA92320@davejwatson-mba.local> References: <20180320024510.7408-1-saeedm@mellanox.com> <20180320024510.7408-7-saeedm@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20180320024510.7408-7-saeedm@mellanox.com> Sender: netdev-owner@vger.kernel.org List-ID: On 03/19/18 07:45 PM, Saeed Mahameed wrote: > +#define TLS_OFFLOAD_CONTEXT_SIZE \ > + (ALIGN(sizeof(struct tls_offload_context), sizeof(void *)) + \ > + TLS_DRIVER_STATE_SIZE) > + > + pfrag = sk_page_frag(sk); > + > + /* KTLS_TLS_HEADER_SIZE is not counted as part of the TLS record, and I think the define is actually TLS_HEADER_SIZE, no KTLS_ prefix > + memcpy(ctx->iv + TLS_CIPHER_AES_GCM_128_SALT_SIZE, iv, iv_size); > + > + ctx->rec_seq_size = rec_seq_size; > + /* worst case is: > + * MAX_SKB_FRAGS in tls_record_info > + * MAX_SKB_FRAGS + 1 in SKB head an frags. spelling > +int tls_sw_fallback_init(struct sock *sk, > + struct tls_offload_context *offload_ctx, > + struct tls_crypto_info *crypto_info) > +{ > + int rc; > + const u8 *key; > + > + offload_ctx->aead_send = > + crypto_alloc_aead("gcm(aes)", 0, CRYPTO_ALG_ASYNC); in tls_sw we went with async + crypto_wait_req, any reason to not do that here? Otherwise I think you still get the software gcm on x86 instead of aesni without additional changes. > diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c > index d824d548447e..e0dface33017 100644 > --- a/net/tls/tls_main.c > +++ b/net/tls/tls_main.c > @@ -54,6 +54,9 @@ enum { > enum { > TLS_BASE_TX, > TLS_SW_TX, > +#ifdef CONFIG_TLS_DEVICE > + TLS_HW_TX, > +#endif > TLS_NUM_CONFIG, > }; I have posted SW_RX patches, do you forsee any issues with SW_RX + HW_TX? Thanks