From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Belloni Subject: [PATCH net-next 2/8] dt-bindings: net: add DT bindings for Microsemi MIIM Date: Fri, 23 Mar 2018 21:11:11 +0100 Message-ID: <20180323201117.8416-3-alexandre.belloni@bootlin.com> References: <20180323201117.8416-1-alexandre.belloni@bootlin.com> Cc: Allan Nielsen , razvan.stefanescu@nxp.com, po.liu@nxp.com, Thomas Petazzoni , Andrew Lunn , Florian Fainelli , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Alexandre Belloni , Rob Herring To: "David S . Miller" Return-path: In-Reply-To: <20180323201117.8416-1-alexandre.belloni@bootlin.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org DT bindings for the Microsemi MII Management Controller found on Microsemi SoCs Cc: Rob Herring Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/net/mscc-miim.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/mscc-miim.txt diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt new file mode 100644 index 000000000000..711ac9ab853c --- /dev/null +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -0,0 +1,25 @@ +Microsemi MII Management Controller (MIIM) / MDIO +================================================= + +Properties: +- compatible: must be "mscc,ocelot-miim" +- reg: The base address of the MDIO bus controller register bank. Optionally, a + second register bank can be defined if there is an associated reset register + for internal PHYs +- #address-cells: Must be <1>. +- #size-cells: Must be <0>. MDIO addresses have no size component. + +Typically an MDIO bus might have several children. + +Example: + mdio@107009c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x107009c 0x36>, <0x10700f0 0x8>; + interrupts = <14>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; -- 2.16.2