From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shahed Shaikh Subject: [PATCH net 1/1] qed: Fix mask for physical address in ILT entry Date: Mon, 21 May 2018 12:31:47 -0700 Message-ID: <20180521193147.18628-1-shahed.shaikh@cavium.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , To: Return-path: Received: from mail-bn3nam01on0088.outbound.protection.outlook.com ([104.47.33.88]:59254 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750942AbeEUTcI (ORCPT ); Mon, 21 May 2018 15:32:08 -0400 Sender: netdev-owner@vger.kernel.org List-ID: ILT entry requires 12 bit right shifted physical address. Existing mask for ILT entry of physical address i.e. ILT_ENTRY_PHY_ADDR_MASK is not sufficient to handle 64bit address because upper 8 bits of 64 bit address were getting masked which resulted in completer abort error on PCIe bus due to invalid address. Fix that mask to handle 64bit physical address. Fixes: fe56b9e6a8d9 ("qed: Add module with basic common support") Signed-off-by: Shahed Shaikh Signed-off-by: Ariel Elior --- drivers/net/ethernet/qlogic/qed/qed_cxt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c index 00f41c1..820b226 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c +++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c @@ -77,7 +77,7 @@ #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET /* ILT entry structure */ -#define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL +#define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12) #define ILT_ENTRY_PHY_ADDR_SHIFT 0 #define ILT_ENTRY_VALID_MASK 0x1ULL #define ILT_ENTRY_VALID_SHIFT 52 -- 1.7.1