* [PATCH V4 1/8] net: ethernet: stmmac: add adaptation for stm32mp157c.
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-24 7:24 ` Alexandre Torgue
2018-05-23 15:47 ` [PATCH V4 2/8] dt-bindings: stm32-dwmac: add support of MPU families Christophe Roullier
` (8 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
Glue codes to support stm32mp157c device and stay
compatible with stm32 mcu family
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 270 ++++++++++++++++++++--
1 file changed, 255 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 9e6db16..f51e327 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -16,49 +16,183 @@
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/stmmac.h>
#include "stmmac_platform.h"
-#define MII_PHY_SEL_MASK BIT(23)
+#define SYSCFG_MCU_ETH_MASK BIT(23)
+#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)
+
+#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
+#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
+#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
+#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
+#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
+#define SYSCFG_PMCR_ETH_SEL_GMII 0
+#define SYSCFG_MCU_ETH_SEL_MII 0
+#define SYSCFG_MCU_ETH_SEL_RMII 1
struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
+ struct clk *clk_eth_ck;
+ struct clk *clk_ethstp;
+ struct clk *syscfg_clk;
+ bool int_phyclk; /* Clock from RCC to drive PHY */
u32 mode_reg; /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
+ const struct stm32_ops *ops;
+ struct device *dev;
+};
+
+struct stm32_ops {
+ int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
+ int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
+ int (*suspend)(struct stm32_dwmac *dwmac);
+ void (*resume)(struct stm32_dwmac *dwmac);
+ int (*parse_data)(struct stm32_dwmac *dwmac,
+ struct device *dev);
+ u32 syscfg_eth_mask;
};
static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
- u32 reg = dwmac->mode_reg;
- u32 val;
int ret;
- val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
- ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
- if (ret)
- return ret;
+ if (dwmac->ops->set_mode) {
+ ret = dwmac->ops->set_mode(plat_dat);
+ if (ret)
+ return ret;
+ }
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
- ret = clk_prepare_enable(dwmac->clk_rx);
- if (ret)
- clk_disable_unprepare(dwmac->clk_tx);
+ if (!dwmac->dev->power.is_suspended) {
+ ret = clk_prepare_enable(dwmac->clk_rx);
+ if (ret) {
+ clk_disable_unprepare(dwmac->clk_tx);
+ return ret;
+ }
+ }
+
+ if (dwmac->ops->clk_prepare) {
+ ret = dwmac->ops->clk_prepare(dwmac, true);
+ if (ret) {
+ clk_disable_unprepare(dwmac->clk_rx);
+ clk_disable_unprepare(dwmac->clk_tx);
+ }
+ }
return ret;
}
+static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+ int ret = 0;
+
+ if (prepare) {
+ ret = clk_prepare_enable(dwmac->syscfg_clk);
+ if (ret)
+ return ret;
+
+ if (dwmac->int_phyclk) {
+ ret = clk_prepare_enable(dwmac->clk_eth_ck);
+ if (ret) {
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ return ret;
+ }
+ }
+ } else {
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ if (dwmac->int_phyclk)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
+ }
+ return ret;
+}
+
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ u32 reg = dwmac->mode_reg;
+ int val;
+
+ switch (plat_dat->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = SYSCFG_PMCR_ETH_SEL_MII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ val = SYSCFG_PMCR_ETH_SEL_GMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val = SYSCFG_PMCR_ETH_SEL_RMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val = SYSCFG_PMCR_ETH_SEL_RGMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
+ break;
+ default:
+ pr_debug("SYSCFG init : Do not manage %d interface\n",
+ plat_dat->interface);
+ /* Do not manage others interfaces */
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(dwmac->regmap, reg,
+ dwmac->ops->syscfg_eth_mask, val);
+}
+
+static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ u32 reg = dwmac->mode_reg;
+ int val;
+
+ switch (plat_dat->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = SYSCFG_MCU_ETH_SEL_MII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val = SYSCFG_MCU_ETH_SEL_RMII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
+ break;
+ default:
+ pr_debug("SYSCFG init : Do not manage %d interface\n",
+ plat_dat->interface);
+ /* Do not manage others interfaces */
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(dwmac->regmap, reg,
+ dwmac->ops->syscfg_eth_mask, val);
+}
+
static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
{
clk_disable_unprepare(dwmac->clk_tx);
clk_disable_unprepare(dwmac->clk_rx);
+
+ if (dwmac->ops->clk_prepare)
+ dwmac->ops->clk_prepare(dwmac, false);
}
static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
@@ -70,15 +204,22 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
/* Get TX/RX clocks */
dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
if (IS_ERR(dwmac->clk_tx)) {
- dev_err(dev, "No tx clock provided...\n");
+ dev_err(dev, "No ETH Tx clock provided...\n");
return PTR_ERR(dwmac->clk_tx);
}
+
dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
if (IS_ERR(dwmac->clk_rx)) {
- dev_err(dev, "No rx clock provided...\n");
+ dev_err(dev, "No ETH Rx clock provided...\n");
return PTR_ERR(dwmac->clk_rx);
}
+ if (dwmac->ops->parse_data) {
+ err = dwmac->ops->parse_data(dwmac, dev);
+ if (err)
+ return err;
+ }
+
/* Get mode register */
dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
if (IS_ERR(dwmac->regmap))
@@ -91,11 +232,46 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
return err;
}
+static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+
+ dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
+
+ /* Check if internal clk from RCC selected */
+ if (dwmac->int_phyclk) {
+ /* Get ETH_CLK clocks */
+ dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
+ if (IS_ERR(dwmac->clk_eth_ck)) {
+ dev_err(dev, "No ETH CK clock provided...\n");
+ return PTR_ERR(dwmac->clk_eth_ck);
+ }
+ }
+
+ /* Clock used for low power mode */
+ dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
+ if (IS_ERR(dwmac->clk_ethstp)) {
+ dev_err(dev, "No ETH peripheral clock provided for CStop mode ...\n");
+ return PTR_ERR(dwmac->clk_ethstp);
+ }
+
+ /* Clock for sysconfig */
+ dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
+ if (IS_ERR(dwmac->syscfg_clk)) {
+ dev_err(dev, "No syscfg clock provided...\n");
+ return PTR_ERR(dwmac->syscfg_clk);
+ }
+
+ return 0;
+}
+
static int stm32_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct stm32_dwmac *dwmac;
+ const struct stm32_ops *data;
int ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -112,6 +288,16 @@ static int stm32_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt;
}
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev, "no of match data provided\n");
+ ret = -EINVAL;
+ goto err_remove_config_dt;
+ }
+
+ dwmac->ops = data;
+ dwmac->dev = &pdev->dev;
+
ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Unable to parse OF data\n");
@@ -149,15 +335,48 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
return ret;
}
+static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
+{
+ int ret = 0;
+
+ ret = clk_prepare_enable(dwmac->clk_ethstp);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(dwmac->clk_tx);
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ if (dwmac->int_phyclk)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
+
+ return ret;
+}
+
+static void stm32mp1_resume(struct stm32_dwmac *dwmac)
+{
+ clk_disable_unprepare(dwmac->clk_ethstp);
+}
+
+static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
+{
+ clk_disable_unprepare(dwmac->clk_tx);
+ clk_disable_unprepare(dwmac->clk_rx);
+
+ return 0;
+}
+
#ifdef CONFIG_PM_SLEEP
static int stm32_dwmac_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
+ struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
+
int ret;
ret = stmmac_suspend(dev);
- stm32_dwmac_clk_disable(priv->plat->bsp_priv);
+
+ if (dwmac->ops->suspend)
+ ret = dwmac->ops->suspend(dwmac);
return ret;
}
@@ -166,8 +385,12 @@ static int stm32_dwmac_resume(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
+ struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
int ret;
+ if (dwmac->ops->resume)
+ dwmac->ops->resume(dwmac);
+
ret = stm32_dwmac_init(priv->plat);
if (ret)
return ret;
@@ -181,8 +404,24 @@ static int stm32_dwmac_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
stm32_dwmac_suspend, stm32_dwmac_resume);
+static struct stm32_ops stm32mcu_dwmac_data = {
+ .set_mode = stm32mcu_set_mode,
+ .suspend = stm32mcu_suspend,
+ .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
+};
+
+static struct stm32_ops stm32mp1_dwmac_data = {
+ .set_mode = stm32mp1_set_mode,
+ .clk_prepare = stm32mp1_clk_prepare,
+ .suspend = stm32mp1_suspend,
+ .resume = stm32mp1_resume,
+ .parse_data = stm32mp1_parse_data,
+ .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
+};
+
static const struct of_device_id stm32_dwmac_match[] = {
- { .compatible = "st,stm32-dwmac"},
+ { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
+ { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
{ }
};
MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
@@ -199,5 +438,6 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
module_platform_driver(stm32_dwmac_driver);
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
-MODULE_DESCRIPTION("STMicroelectronics MCU DWMAC Specific Glue layer");
+MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH V4 1/8] net: ethernet: stmmac: add adaptation for stm32mp157c.
2018-05-23 15:47 ` [PATCH V4 1/8] net: ethernet: stmmac: add adaptation for stm32mp157c Christophe Roullier
@ 2018-05-24 7:24 ` Alexandre Torgue
0 siblings, 0 replies; 15+ messages in thread
From: Alexandre Torgue @ 2018-05-24 7:24 UTC (permalink / raw)
To: Christophe Roullier, mark.rutland, mcoquelin.stm32,
peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, andrew
Hi,
On 05/23/2018 05:47 PM, Christophe Roullier wrote:
> Glue codes to support stm32mp157c device and stay
> compatible with stm32 mcu family
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
> drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 270 ++++++++++++++++++++--
> 1 file changed, 255 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> index 9e6db16..f51e327 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> @@ -16,49 +16,183 @@
> #include <linux/of_net.h>
> #include <linux/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_wakeirq.h>
> #include <linux/regmap.h>
> #include <linux/slab.h>
> #include <linux/stmmac.h>
>
> #include "stmmac_platform.h"
>
> -#define MII_PHY_SEL_MASK BIT(23)
> +#define SYSCFG_MCU_ETH_MASK BIT(23)
> +#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)
> +
> +#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
> +#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
> +#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
> +#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
> +#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
> +#define SYSCFG_PMCR_ETH_SEL_GMII 0
> +#define SYSCFG_MCU_ETH_SEL_MII 0
> +#define SYSCFG_MCU_ETH_SEL_RMII 1
>
> struct stm32_dwmac {
> struct clk *clk_tx;
> struct clk *clk_rx;
> + struct clk *clk_eth_ck;
> + struct clk *clk_ethstp;
> + struct clk *syscfg_clk;
> + bool int_phyclk; /* Clock from RCC to drive PHY */
> u32 mode_reg; /* MAC glue-logic mode register */
> struct regmap *regmap;
> u32 speed;
> + const struct stm32_ops *ops;
> + struct device *dev;
> +};
> +
> +struct stm32_ops {
> + int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
> + int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
> + int (*suspend)(struct stm32_dwmac *dwmac);
> + void (*resume)(struct stm32_dwmac *dwmac);
> + int (*parse_data)(struct stm32_dwmac *dwmac,
> + struct device *dev);
> + u32 syscfg_eth_mask;
> };
>
> static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
> {
> struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
> - u32 reg = dwmac->mode_reg;
> - u32 val;
> int ret;
>
> - val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
> - ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
> - if (ret)
> - return ret;
> + if (dwmac->ops->set_mode) {
> + ret = dwmac->ops->set_mode(plat_dat);
> + if (ret)
> + return ret;
> + }
>
> ret = clk_prepare_enable(dwmac->clk_tx);
> if (ret)
> return ret;
>
> - ret = clk_prepare_enable(dwmac->clk_rx);
> - if (ret)
> - clk_disable_unprepare(dwmac->clk_tx);
> + if (!dwmac->dev->power.is_suspended) {
> + ret = clk_prepare_enable(dwmac->clk_rx);
> + if (ret) {
> + clk_disable_unprepare(dwmac->clk_tx);
> + return ret;
> + }
> + }
> +
> + if (dwmac->ops->clk_prepare) {
> + ret = dwmac->ops->clk_prepare(dwmac, true);
> + if (ret) {
> + clk_disable_unprepare(dwmac->clk_rx);
> + clk_disable_unprepare(dwmac->clk_tx);
> + }
> + }
>
> return ret;
> }
>
> +static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
> +{
> + int ret = 0;
> +
> + if (prepare) {
> + ret = clk_prepare_enable(dwmac->syscfg_clk);
> + if (ret)
> + return ret;
> +
> + if (dwmac->int_phyclk) {
> + ret = clk_prepare_enable(dwmac->clk_eth_ck);
> + if (ret) {
> + clk_disable_unprepare(dwmac->syscfg_clk);
> + return ret;
> + }
> + }
> + } else {
> + clk_disable_unprepare(dwmac->syscfg_clk);
> + if (dwmac->int_phyclk)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
> + }
> + return ret;
> +}
> +
> +static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> +{
> + struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
> + u32 reg = dwmac->mode_reg;
> + int val;
> +
> + switch (plat_dat->interface) {
> + case PHY_INTERFACE_MODE_MII:
> + val = SYSCFG_PMCR_ETH_SEL_MII;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
> + break;
> + case PHY_INTERFACE_MODE_GMII:
> + val = SYSCFG_PMCR_ETH_SEL_GMII;
> + if (dwmac->int_phyclk)
> + val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + val = SYSCFG_PMCR_ETH_SEL_RMII;
> + if (dwmac->int_phyclk)
> + val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
> + break;
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + val = SYSCFG_PMCR_ETH_SEL_RGMII;
> + if (dwmac->int_phyclk)
> + val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
> + break;
> + default:
> + pr_debug("SYSCFG init : Do not manage %d interface\n",
> + plat_dat->interface);
> + /* Do not manage others interfaces */
> + return -EINVAL;
> + }
> +
> + return regmap_update_bits(dwmac->regmap, reg,
> + dwmac->ops->syscfg_eth_mask, val);
> +}
> +
> +static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
> +{
> + struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
> + u32 reg = dwmac->mode_reg;
> + int val;
> +
> + switch (plat_dat->interface) {
> + case PHY_INTERFACE_MODE_MII:
> + val = SYSCFG_MCU_ETH_SEL_MII;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + val = SYSCFG_MCU_ETH_SEL_RMII;
> + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
> + break;
> + default:
> + pr_debug("SYSCFG init : Do not manage %d interface\n",
> + plat_dat->interface);
> + /* Do not manage others interfaces */
> + return -EINVAL;
> + }
> +
> + return regmap_update_bits(dwmac->regmap, reg,
> + dwmac->ops->syscfg_eth_mask, val);
> +}
> +
> static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
> {
> clk_disable_unprepare(dwmac->clk_tx);
> clk_disable_unprepare(dwmac->clk_rx);
> +
> + if (dwmac->ops->clk_prepare)
> + dwmac->ops->clk_prepare(dwmac, false);
> }
>
> static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
> @@ -70,15 +204,22 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
> /* Get TX/RX clocks */
> dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
> if (IS_ERR(dwmac->clk_tx)) {
> - dev_err(dev, "No tx clock provided...\n");
> + dev_err(dev, "No ETH Tx clock provided...\n");
> return PTR_ERR(dwmac->clk_tx);
> }
> +
> dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
> if (IS_ERR(dwmac->clk_rx)) {
> - dev_err(dev, "No rx clock provided...\n");
> + dev_err(dev, "No ETH Rx clock provided...\n");
> return PTR_ERR(dwmac->clk_rx);
> }
>
> + if (dwmac->ops->parse_data) {
> + err = dwmac->ops->parse_data(dwmac, dev);
> + if (err)
> + return err;
> + }
> +
> /* Get mode register */
> dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
> if (IS_ERR(dwmac->regmap))
> @@ -91,11 +232,46 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
> return err;
> }
>
> +static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
> + struct device *dev)
> +{
> + struct device_node *np = dev->of_node;
> +
> + dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
> +
> + /* Check if internal clk from RCC selected */
> + if (dwmac->int_phyclk) {
> + /* Get ETH_CLK clocks */
> + dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
> + if (IS_ERR(dwmac->clk_eth_ck)) {
> + dev_err(dev, "No ETH CK clock provided...\n");
> + return PTR_ERR(dwmac->clk_eth_ck);
> + }
> + }
> +
> + /* Clock used for low power mode */
> + dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
> + if (IS_ERR(dwmac->clk_ethstp)) {
> + dev_err(dev, "No ETH peripheral clock provided for CStop mode ...\n");
> + return PTR_ERR(dwmac->clk_ethstp);
> + }
> +
> + /* Clock for sysconfig */
> + dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
> + if (IS_ERR(dwmac->syscfg_clk)) {
> + dev_err(dev, "No syscfg clock provided...\n");
> + return PTR_ERR(dwmac->syscfg_clk);
> + }
> +
> + return 0;
> +}
> +
> static int stm32_dwmac_probe(struct platform_device *pdev)
> {
> struct plat_stmmacenet_data *plat_dat;
> struct stmmac_resources stmmac_res;
> struct stm32_dwmac *dwmac;
> + const struct stm32_ops *data;
> int ret;
>
> ret = stmmac_get_platform_resources(pdev, &stmmac_res);
> @@ -112,6 +288,16 @@ static int stm32_dwmac_probe(struct platform_device *pdev)
> goto err_remove_config_dt;
> }
>
> + data = of_device_get_match_data(&pdev->dev);
> + if (!data) {
> + dev_err(&pdev->dev, "no of match data provided\n");
> + ret = -EINVAL;
> + goto err_remove_config_dt;
> + }
> +
> + dwmac->ops = data;
> + dwmac->dev = &pdev->dev;
> +
> ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
> if (ret) {
> dev_err(&pdev->dev, "Unable to parse OF data\n");
> @@ -149,15 +335,48 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
> return ret;
> }
>
> +static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
> +{
> + int ret = 0;
> +
> + ret = clk_prepare_enable(dwmac->clk_ethstp);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(dwmac->clk_tx);
> + clk_disable_unprepare(dwmac->syscfg_clk);
> + if (dwmac->int_phyclk)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
> +
> + return ret;
> +}
> +
> +static void stm32mp1_resume(struct stm32_dwmac *dwmac)
> +{
> + clk_disable_unprepare(dwmac->clk_ethstp);
> +}
> +
> +static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
> +{
> + clk_disable_unprepare(dwmac->clk_tx);
> + clk_disable_unprepare(dwmac->clk_rx);
> +
> + return 0;
> +}
> +
> #ifdef CONFIG_PM_SLEEP
> static int stm32_dwmac_suspend(struct device *dev)
> {
> struct net_device *ndev = dev_get_drvdata(dev);
> struct stmmac_priv *priv = netdev_priv(ndev);
> + struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
> +
> int ret;
>
> ret = stmmac_suspend(dev);
> - stm32_dwmac_clk_disable(priv->plat->bsp_priv);
> +
> + if (dwmac->ops->suspend)
> + ret = dwmac->ops->suspend(dwmac);
>
> return ret;
> }
> @@ -166,8 +385,12 @@ static int stm32_dwmac_resume(struct device *dev)
> {
> struct net_device *ndev = dev_get_drvdata(dev);
> struct stmmac_priv *priv = netdev_priv(ndev);
> + struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
> int ret;
>
> + if (dwmac->ops->resume)
> + dwmac->ops->resume(dwmac);
> +
> ret = stm32_dwmac_init(priv->plat);
> if (ret)
> return ret;
> @@ -181,8 +404,24 @@ static int stm32_dwmac_resume(struct device *dev)
> static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
> stm32_dwmac_suspend, stm32_dwmac_resume);
>
> +static struct stm32_ops stm32mcu_dwmac_data = {
> + .set_mode = stm32mcu_set_mode,
> + .suspend = stm32mcu_suspend,
> + .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
> +};
> +
> +static struct stm32_ops stm32mp1_dwmac_data = {
> + .set_mode = stm32mp1_set_mode,
> + .clk_prepare = stm32mp1_clk_prepare,
> + .suspend = stm32mp1_suspend,
> + .resume = stm32mp1_resume,
> + .parse_data = stm32mp1_parse_data,
> + .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
> +};
> +
> static const struct of_device_id stm32_dwmac_match[] = {
> - { .compatible = "st,stm32-dwmac"},
> + { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
> + { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
> @@ -199,5 +438,6 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
> module_platform_driver(stm32_dwmac_driver);
>
> MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
> -MODULE_DESCRIPTION("STMicroelectronics MCU DWMAC Specific Glue layer");
> +MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
> MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH V4 2/8] dt-bindings: stm32-dwmac: add support of MPU families
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 1/8] net: ethernet: stmmac: add adaptation for stm32mp157c Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 3/8] ARM: dts: stm32: add ethernet pins to stm32mp157c Christophe Roullier
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
Add description for Ethernet MPU families fields
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 489dbcb..1341012 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -6,14 +6,28 @@ Please see stmmac.txt for the other unchanged properties.
The device node has following properties.
Required properties:
-- compatible: Should be "st,stm32-dwmac" to select glue, and
+- compatible: For MCU family should be "st,stm32-dwmac" to select glue, and
"snps,dwmac-3.50a" to select IP version.
+ For MPU family should be "st,stm32mp1-dwmac" to select
+ glue, and "snps,dwmac-4.20a" to select IP version.
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: Should be "stmmaceth" for the host clock.
Should be "mac-clk-tx" for the MAC TX clock.
Should be "mac-clk-rx" for the MAC RX clock.
+ For MPU family need to add also "ethstp" for power mode clock and,
+ "syscfg-clk" for SYSCFG clock.
+- interrupt-names: Should contain a list of interrupt names corresponding to
+ the interrupts in the interrupts property, if available.
+ Should be "macirq" for the main MAC IRQ
+ Should be "eth_wake_irq" for the IT which wake up system
- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register.
+ encompases the glue register, and the offset of the control register.
+
+Optional properties:
+- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
+- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock
+ by RCC
+
Example:
ethernet@40028000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V4 3/8] ARM: dts: stm32: add ethernet pins to stm32mp157c
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 1/8] net: ethernet: stmmac: add adaptation for stm32mp157c Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 2/8] dt-bindings: stm32-dwmac: add support of MPU families Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 4/8] ARM: dts: stm32: Add syscfg on stm32mp1 Christophe Roullier
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
Add ethernet pins on stm32mp157c.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 46 +++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 6f044100..cf83eb244 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -158,6 +158,52 @@
bias-disable;
};
};
+
+ ethernet0_rgmii_pins_a: rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
};
pinctrl_z: pin-controller-z {
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V4 4/8] ARM: dts: stm32: Add syscfg on stm32mp1
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (2 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 3/8] ARM: dts: stm32: add ethernet pins to stm32mp157c Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 5/8] ARM: dts: stm32: Add ethernet dwmac " Christophe Roullier
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
System configuration controller is mainly used to manage
the compensation cell and other IOs and system related
settings.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
arch/arm/boot/dts/stm32mp157c.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..3db03a2 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -167,6 +167,11 @@
#reset-cells = <1>;
};
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ };
+
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V4 5/8] ARM: dts: stm32: Add ethernet dwmac on stm32mp1
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (3 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 4/8] ARM: dts: stm32: Add syscfg on stm32mp1 Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-06-26 13:21 ` Alexandre Torgue
2018-05-23 15:47 ` [PATCH V4 6/8] net: stmmac: add dwmac-4.20a compatible Christophe Roullier
` (4 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
Add Ethernet support (Synopsys MAC IP 4.20a) on stm32mp1 SOC.
Enable feature supported by the stmmac driver, such as TSO.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
arch/arm/boot/dts/stm32mp157c.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 3db03a2..ea7b6cb 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -179,5 +179,35 @@
clocks = <&rcc USART1_K>;
status = "disabled";
};
+
+ stmmac_axi_config_0: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ ethernet0: ethernet@5800a000 {
+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_NONE>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "syscfg-clk";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
+ <&rcc ETHSTP>,
+ <&rcc SYSCFG>;
+ st,syscon = <&syscfg 0x4>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_0>;
+ snps,tso;
+ status = "disabled";
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH V4 5/8] ARM: dts: stm32: Add ethernet dwmac on stm32mp1
2018-05-23 15:47 ` [PATCH V4 5/8] ARM: dts: stm32: Add ethernet dwmac " Christophe Roullier
@ 2018-06-26 13:21 ` Alexandre Torgue
0 siblings, 0 replies; 15+ messages in thread
From: Alexandre Torgue @ 2018-06-26 13:21 UTC (permalink / raw)
To: Christophe Roullier, mark.rutland, mcoquelin.stm32,
peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, andrew
Hi christophe
On 05/23/2018 05:47 PM, Christophe Roullier wrote:
> Add Ethernet support (Synopsys MAC IP 4.20a) on stm32mp1 SOC.
> Enable feature supported by the stmmac driver, such as TSO.
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
> arch/arm/boot/dts/stm32mp157c.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
> index 3db03a2..ea7b6cb 100644
> --- a/arch/arm/boot/dts/stm32mp157c.dtsi
> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi
> @@ -179,5 +179,35 @@
> clocks = <&rcc USART1_K>;
> status = "disabled";
> };
> +
> + stmmac_axi_config_0: stmmac-axi-config {
> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> +
> + ethernet0: ethernet@5800a000 {
> + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
> + reg = <0x5800a000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_NONE>;
IRQ_TYPE_NONE souldn't be used. Please provide edge sensitiv or level
sensitic type.
> + interrupt-names = "macirq";
> + clock-names = "stmmaceth",
> + "mac-clk-tx",
> + "mac-clk-rx",
> + "ethstp",
> + "syscfg-clk";
> + clocks = <&rcc ETHMAC>,
> + <&rcc ETHTX>,
> + <&rcc ETHRX>,
> + <&rcc ETHSTP>,
> + <&rcc SYSCFG>;
> + st,syscon = <&syscfg 0x4>;
> + snps,mixed-burst;
> + snps,pbl = <2>;
> + snps,axi-config = <&stmmac_axi_config_0>;
> + snps,tso;
> + status = "disabled";
> + };
> };
> };
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH V4 6/8] net: stmmac: add dwmac-4.20a compatible
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (4 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 5/8] ARM: dts: stm32: Add ethernet dwmac " Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 7/8] ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1 Christophe Roullier
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
Manage dwmac-4.20a version from synopsys
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index ebd3e5f..6d141f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -472,7 +472,8 @@ struct plat_stmmacenet_data *
}
if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
- of_device_is_compatible(np, "snps,dwmac-4.10a")) {
+ of_device_is_compatible(np, "snps,dwmac-4.10a") ||
+ of_device_is_compatible(np, "snps,dwmac-4.20a")) {
plat->has_gmac4 = 1;
plat->has_gmac = 0;
plat->pmt = 1;
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V4 7/8] ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (5 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 6/8] net: stmmac: add dwmac-4.20a compatible Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 15:47 ` [PATCH V4 8/8] dt-bindings: stm32: add compatible for syscon Christophe Roullier
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
MAC is connected to a PHY in RGMII mode.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
arch/arm/boot/dts/stm32mp157c-ev1.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 57e6dbc..a7fee5c 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -17,5 +17,25 @@
aliases {
serial0 = &uart4;
+ ethernet0 = ðernet0;
+ };
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V4 8/8] dt-bindings: stm32: add compatible for syscon
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (6 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 7/8] ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1 Christophe Roullier
@ 2018-05-23 15:47 ` Christophe Roullier
2018-05-23 19:03 ` Rob Herring
2018-05-23 20:08 ` [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 David Miller
2018-06-26 16:31 ` Alexandre Torgue
9 siblings, 1 reply; 15+ messages in thread
From: Christophe Roullier @ 2018-05-23 15:47 UTC (permalink / raw)
To: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, christophe.roullier, andrew
This patch describes syscon DT bindings.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
Documentation/devicetree/bindings/arm/stm32.txt | 10 ----------
.../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++++++++++++++
Documentation/devicetree/bindings/arm/stm32/stm32.txt | 10 ++++++++++
3 files changed, 24 insertions(+), 10 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/stm32.txt
create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32.txt
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
deleted file mode 100644
index 6808ed9..0000000
--- a/Documentation/devicetree/bindings/arm/stm32.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-STMicroelectronics STM32 Platforms Device Tree Bindings
-
-Each device tree must specify which STM32 SoC it uses,
-using one of the following compatible strings:
-
- st,stm32f429
- st,stm32f469
- st,stm32f746
- st,stm32h743
- st,stm32mp157
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
new file mode 100644
index 0000000..99980ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 Platforms System Controller
+
+Properties:
+ - compatible : should contain two values. First value must be :
+ - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
+ second value must be always "syscon".
+ - reg : offset and length of the register set.
+
+ Example:
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.txt b/Documentation/devicetree/bindings/arm/stm32/stm32.txt
new file mode 100644
index 0000000..6808ed9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.txt
@@ -0,0 +1,10 @@
+STMicroelectronics STM32 Platforms Device Tree Bindings
+
+Each device tree must specify which STM32 SoC it uses,
+using one of the following compatible strings:
+
+ st,stm32f429
+ st,stm32f469
+ st,stm32f746
+ st,stm32h743
+ st,stm32mp157
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH V4 8/8] dt-bindings: stm32: add compatible for syscon
2018-05-23 15:47 ` [PATCH V4 8/8] dt-bindings: stm32: add compatible for syscon Christophe Roullier
@ 2018-05-23 19:03 ` Rob Herring
0 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2018-05-23 19:03 UTC (permalink / raw)
To: Christophe Roullier
Cc: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro,
devicetree, linux-arm-kernel, netdev, andrew
On Wed, May 23, 2018 at 05:47:59PM +0200, Christophe Roullier wrote:
> This patch describes syscon DT bindings.
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
> Documentation/devicetree/bindings/arm/stm32.txt | 10 ----------
> .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++++++++++++++
> Documentation/devicetree/bindings/arm/stm32/stm32.txt | 10 ++++++++++
> 3 files changed, 24 insertions(+), 10 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/stm32.txt
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32.txt
In the future, use the -M option so file moves don't show any diff.
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (7 preceding siblings ...)
2018-05-23 15:47 ` [PATCH V4 8/8] dt-bindings: stm32: add compatible for syscon Christophe Roullier
@ 2018-05-23 20:08 ` David Miller
2018-05-24 7:22 ` Alexandre Torgue
2018-06-26 16:31 ` Alexandre Torgue
9 siblings, 1 reply; 15+ messages in thread
From: David Miller @ 2018-05-23 20:08 UTC (permalink / raw)
To: christophe.roullier
Cc: mark.rutland, mcoquelin.stm32, alexandre.torgue, peppe.cavallaro,
devicetree, linux-arm-kernel, netdev, andrew
From: Christophe Roullier <christophe.roullier@st.com>
Date: Wed, 23 May 2018 17:47:51 +0200
> Patches to have Ethernet support on stm32mp1
> Changelog:
> Remark from Rob Herring
> Move Documentation/devicetree/bindings/arm/stm32.txt in
> Documentation/devicetree/bindings/arm/stm32/stm32.txt and create
> Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
>
> Replace also in arch/arm/boot/dts/stm32mp157c.dtsi, syscfg: system-config@50020000
> with syscfg: syscon@50020000syscfg: system-config@50020000
Probably the DTS file updates need to go in via the ARM tree, not
mine.
Can you respin a net-next targetted series that has just the driver
code and device tree binding updates?
Thank you!
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1
2018-05-23 20:08 ` [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 David Miller
@ 2018-05-24 7:22 ` Alexandre Torgue
0 siblings, 0 replies; 15+ messages in thread
From: Alexandre Torgue @ 2018-05-24 7:22 UTC (permalink / raw)
To: David Miller, christophe.roullier
Cc: mark.rutland, mcoquelin.stm32, peppe.cavallaro, devicetree,
linux-arm-kernel, netdev, andrew
On 05/23/2018 10:08 PM, David Miller wrote:
> From: Christophe Roullier <christophe.roullier@st.com>
> Date: Wed, 23 May 2018 17:47:51 +0200
>
>> Patches to have Ethernet support on stm32mp1
>> Changelog:
>> Remark from Rob Herring
>> Move Documentation/devicetree/bindings/arm/stm32.txt in
>> Documentation/devicetree/bindings/arm/stm32/stm32.txt and create
>> Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
>>
>> Replace also in arch/arm/boot/dts/stm32mp157c.dtsi, syscfg: system-config@50020000
>> with syscfg: syscon@50020000syscfg: system-config@50020000
>
> Probably the DTS file updates need to go in via the ARM tree, not
> mine.
Yes I will take them in my tree
>
> Can you respin a net-next targetted series that has just the driver
> code and device tree binding updates?
>
> Thank you!
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1
2018-05-23 15:47 [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 Christophe Roullier
` (8 preceding siblings ...)
2018-05-23 20:08 ` [PATCH V4 0/8] net: ethernet: stmmac: add support for stm32mp1 David Miller
@ 2018-06-26 16:31 ` Alexandre Torgue
9 siblings, 0 replies; 15+ messages in thread
From: Alexandre Torgue @ 2018-06-26 16:31 UTC (permalink / raw)
To: Christophe Roullier, mark.rutland, mcoquelin.stm32,
peppe.cavallaro
Cc: devicetree, linux-arm-kernel, netdev, andrew
Hi Christophe,
On 05/23/2018 05:47 PM, Christophe Roullier wrote:
> Patches to have Ethernet support on stm32mp1
> Changelog:
> Remark from Rob Herring
> Move Documentation/devicetree/bindings/arm/stm32.txt in
> Documentation/devicetree/bindings/arm/stm32/stm32.txt and create
> Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
>
> Replace also in arch/arm/boot/dts/stm32mp157c.dtsi, syscfg: system-config@50020000
> with syscfg: syscon@50020000syscfg: system-config@50020000
>
> Christophe Roullier (8):
> net: ethernet: stmmac: add adaptation for stm32mp157c.
> dt-bindings: stm32-dwmac: add support of MPU families
> ARM: dts: stm32: add ethernet pins to stm32mp157c
> ARM: dts: stm32: Add syscfg on stm32mp1
> ARM: dts: stm32: Add ethernet dwmac on stm32mp1
> net: stmmac: add dwmac-4.20a compatible
> ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1
> dt-bindings: stm32: add compatible for syscon
>
> Documentation/devicetree/bindings/arm/stm32.txt | 10 -
> .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++
> .../devicetree/bindings/arm/stm32/stm32.txt | 10 +
> .../devicetree/bindings/net/stm32-dwmac.txt | 18 +-
> arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 46 ++++
> arch/arm/boot/dts/stm32mp157c-ev1.dts | 20 ++
> arch/arm/boot/dts/stm32mp157c.dtsi | 35 +++
> drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 270 +++++++++++++++++++--
> .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +-
> 9 files changed, 398 insertions(+), 28 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/stm32.txt
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32.txt
>
As discussed I squashed "ARM: dts: stm32: add ethernet pins to
stm32mp157c" and "ARM: dts: stm32: add support of ethernet on
stm32mp157c-ev1" ans fixed interrupt binding issue.
So DT patches applied on stm32-next.
regards
Alex
^ permalink raw reply [flat|nested] 15+ messages in thread