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From: Andrew Lunn <andrew@lunn.ch>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: davem@davemloft.net,
	Russell King - ARM Linux <linux@armlinux.org.uk>,
	Florian Fainelli <f.fainelli@gmail.com>,
	netdev <netdev@vger.kernel.org>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	"thomas.petazzoni@bootlin.com" <thomas.petazzoni@bootlin.com>,
	Gregory CLEMENT <gregory.clement@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: Link modes representation in phylib
Date: Mon, 18 Jun 2018 17:40:18 +0200	[thread overview]
Message-ID: <20180618154018.GB5865@lunn.ch> (raw)
In-Reply-To: <20180618170224.321f8264@bootlin.com>

On Mon, Jun 18, 2018 at 05:02:24PM +0200, Maxime Chevallier wrote:
> Hello everyone,
> 
> I'm currently working on adding support for 2.5GBaseT on some Marvell
> PHYs (the marvell10g family, including the 88X3310).
> 
> However, phylib doesn't quite support these modes yet. Its stores the
> different supported and advertised modes in u32 fields, which can't
> contain the relevant values for 2500BaseT mode (and all other modes that
> come after the 31st one).

Hi Maxime

Did you look at phylink? I think it already gets this right.  It could
be, any MAC which needs to use > bit 31 should use phylink, not
phylib.

That narrows the problem down to just the PHY drivers. We might be
able to mass convert those. Or maybe we can consider just doing some
conversion work on PHYs which support > 1Gbps?

	   Andrew

  reply	other threads:[~2018-06-18 15:40 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-18 15:02 Link modes representation in phylib Maxime Chevallier
2018-06-18 15:40 ` Andrew Lunn [this message]
2018-06-19  9:30   ` Maxime Chevallier
2018-06-19 15:21     ` Andrew Lunn
2018-06-29 13:26       ` Maxime Chevallier
2018-06-29 13:43         ` Andrew Lunn
2018-06-29 15:09           ` Maxime Chevallier
2018-06-29 15:34             ` Andrew Lunn
2018-06-29 15:39               ` Maxime Chevallier

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