From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Miller Subject: Re: [PATCH v2 2/2] net: macb: Allocate valid memory for TX and RX BD prefetch Date: Sat, 07 Jul 2018 20:55:21 +0900 (KST) Message-ID: <20180707.205521.189537026947491605.davem@davemloft.net> References: <1530859738-11802-1-git-send-email-harini.katakam@xilinx.com> <1530859738-11802-2-git-send-email-harini.katakam@xilinx.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: nicolas.ferre@microchip.com, claudiu.beznea@microchip.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michal.simek@xilinx.com, harinikatakamlinux@gmail.com To: harini.katakam@xilinx.com Return-path: In-Reply-To: <1530859738-11802-2-git-send-email-harini.katakam@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org From: Harini Katakam Date: Fri, 6 Jul 2018 12:18:58 +0530 > GEM version in ZynqMP and most versions greater than r1p07 supports > TX and RX BD prefetch. The number of BDs that can be prefetched is a > HW configurable parameter. For ZynqMP, this parameter is 4. > > When GEM DMA is accessing the last BD in the ring, even before the > BD is processed and the WRAP bit is noticed, it will have prefetched > BDs outside the BD ring. These will not be processed but it is > necessary to have accessible memory after the last BD. Especially > in cases where SMMU is used, memory locations immediately after the > last BD may not have translation tables triggering HRESP errors. Hence > always allocate extra BDs to accommodate for prefetch. > The value of tx/rx bd prefetch for any given SoC version is: > 2 ^ (corresponding field in design config 10 register). > (value of this field >= 1) > > Added a capability flag so that older IP versions that do not have > DCFG10 or this prefetch capability are not affected. > > Signed-off-by: Harini Katakam > Reviewed-by: Claudiu Beznea Applied.