From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: [PATCH 1/4 v1] net: phy: realtek: Support RTL8366RB variant Date: Sat, 14 Jul 2018 11:45:53 +0200 Message-ID: <20180714094556.30791-1-linus.walleij@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: netdev@vger.kernel.org, openwrt-devel@lists.openwrt.org, LEDE Development List , Linus Walleij , =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= , Roman Yeryomin , Colin Leitner , Gabor Juhos To: Andrew Lunn , Vivien Didelot , Florian Fainelli Return-path: Received: from mail-lf0-f68.google.com ([209.85.215.68]:35861 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727785AbeGNKGk (ORCPT ); Sat, 14 Jul 2018 06:06:40 -0400 Received: by mail-lf0-f68.google.com with SMTP id b22-v6so16589560lfa.3 for ; Sat, 14 Jul 2018 02:48:08 -0700 (PDT) Sender: netdev-owner@vger.kernel.org List-ID: The RTL8366RB is an ASIC with five internal PHYs for LAN0..LAN3 and WAN. The PHYs are spawn off the main device so they can be handled in a distributed manner by the Realtek PHY driver. All that is really needed is the power save feature enablement and letting the PHY driver core pick up the IRQ from the switch chip. Cc: Antti Seppälä Cc: Roman Yeryomin Cc: Colin Leitner Cc: Gabor Juhos Cc: Florian Fainelli Signed-off-by: Linus Walleij --- ChangeLog RFCv2->v1 - Correct the PHY power save register from 0x21 to 0x15 as it should be. - Drop the comment about the DSA switch. - Use BIT(12) for power save bit define - Use phy_set_bits() to simplify code - Skip assigning genphy_config_aneg() and genphy_read_status() as this is default anyway ChangeLog RFCv1->RFCv2: - No real changes. --- drivers/net/phy/realtek.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 082fb40c656d..d0d07f22df1f 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -37,6 +37,9 @@ #define RTL8201F_ISR 0x1e #define RTL8201F_IER 0x13 +#define RTL8366RB_POWER_SAVE 0x15 +#define RTL8366RB_POWER_SAVE_ON BIT(12) + MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); MODULE_LICENSE("GPL"); @@ -159,6 +162,24 @@ static int rtl8211b_resume(struct phy_device *phydev) return genphy_resume(phydev); } +static int rtl8366rb_config_init(struct phy_device *phydev) +{ + int ret; + + ret = genphy_config_init(phydev); + if (ret < 0) + return ret; + + ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, + RTL8366RB_POWER_SAVE_ON); + if (ret) { + dev_err(&phydev->mdio.dev, + "error enabling power management\n"); + } + + return ret; +} + static struct phy_driver realtek_drvs[] = { { .phy_id = 0x00008201, @@ -223,6 +244,15 @@ static struct phy_driver realtek_drvs[] = { .resume = genphy_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, + }, { + .phy_id = 0x001cc961, + .name = "RTL8366RB Gigabit Ethernet", + .phy_id_mask = 0x001fffff, + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = &rtl8366rb_config_init, + .suspend = genphy_suspend, + .resume = genphy_resume, }, }; @@ -234,6 +264,7 @@ static struct mdio_device_id __maybe_unused realtek_tbl[] = { { 0x001cc914, 0x001fffff }, { 0x001cc915, 0x001fffff }, { 0x001cc916, 0x001fffff }, + { 0x001cc961, 0x001fffff }, { } }; -- 2.17.1