From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ido Schimmel Subject: [PATCH net-next 1/3] mlxsw: reg: Add QoS Switch Traffic Class Table is Multicast-Aware Register Date: Sun, 5 Aug 2018 09:03:06 +0300 Message-ID: <20180805060308.7862-2-idosch@mellanox.com> References: <20180805060308.7862-1-idosch@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain Cc: davem@davemloft.net, jiri@mellanox.com, petrm@mellanox.com, mlxsw@mellanox.com, Ido Schimmel To: netdev@vger.kernel.org Return-path: Received: from mail-eopbgr20056.outbound.protection.outlook.com ([40.107.2.56]:47952 "EHLO EUR02-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725909AbeHEIHk (ORCPT ); Sun, 5 Aug 2018 04:07:40 -0400 In-Reply-To: <20180805060308.7862-1-idosch@mellanox.com> Sender: netdev-owner@vger.kernel.org List-ID: From: Petr Machata This register configures if the Switch Priority to Traffic Class mapping is based on Multicast packet indication. If so, then multicast packets will get a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by QTCT. Signed-off-by: Petr Machata Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index e2e2f897e98e..6e8b619b769b 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -3509,6 +3509,42 @@ mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); } +/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register + * ------------------------------------------------------------------ + * This register configures if the Switch Priority to Traffic Class mapping is + * based on Multicast packet indication. If so, then multicast packets will get + * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by + * QTCT. + * By default, Switch Priority to Traffic Class mapping is not based on + * Multicast packet indication. + */ +#define MLXSW_REG_QTCTM_ID 0x401A +#define MLXSW_REG_QTCTM_LEN 0x08 + +MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); + +/* reg_qtctm_local_port + * Local port number. + * No support for CPU port. + * Access: Index + */ +MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); + +/* reg_qtctm_mc + * Multicast Mode + * Whether Switch Priority to Traffic Class mapping is based on Multicast packet + * indication (default is 0, not based on Multicast packet indication). + */ +MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); + +static inline void +mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) +{ + MLXSW_REG_ZERO(qtctm, payload); + mlxsw_reg_qtctm_local_port_set(payload, local_port); + mlxsw_reg_qtctm_mc_set(payload, mc); +} + /* PMLP - Ports Module to Local Port Register * ------------------------------------------ * Configures the assignment of modules to local ports. @@ -8726,6 +8762,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(qrwe), MLXSW_REG(qpdsm), MLXSW_REG(qpdpm), + MLXSW_REG(qtctm), MLXSW_REG(pmlp), MLXSW_REG(pmtu), MLXSW_REG(ptys), -- 2.17.1