From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: C45 support and mdiobus_scan Date: Thu, 9 Aug 2018 17:25:02 +0200 Message-ID: <20180809152502.GC20006@lunn.ch> References: <3bbd1d78-b896-2a81-83cf-7dad2f73bae9@synopsys.com> <20180809150309.GA20006@lunn.ch> <568ff5ce-02ac-40f9-ccf7-fa00fb9c6b2a@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "netdev@vger.kernel.org" To: Jose Abreu Return-path: Received: from vps0.lunn.ch ([185.16.172.187]:59981 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730803AbeHIRu2 (ORCPT ); Thu, 9 Aug 2018 13:50:28 -0400 Content-Disposition: inline In-Reply-To: <568ff5ce-02ac-40f9-ccf7-fa00fb9c6b2a@synopsys.com> Sender: netdev-owner@vger.kernel.org List-ID: > > The PCIe core will look in the device tree and when it creates the > > platform device for the i210 on the pcie bus, it points > > pdev->dev.of_node at this node. So long as you are using a platform > > with DT, you can do this. I hope you are not using x86.. > > Yes I am :( Any possible solution for this? Well, DT can be used with x86. I think Edison did that. But i assume your PCIe host is in ACPI, not DT. So getting this linking working will not be easy. There has been some work to add an ACPI binding for PHYs. I don't know if it actually got far enough that you can hack your DSDT to add a PHY. But i'm sure it did not get far enough that you can describe an MDIO bus in DSDT, so it probably is not going to help you. > I guess in ultimate case I will have to switch to ARM based setup. Yes, or MIPS. Andrew