From mboxrd@z Thu Jan 1 00:00:00 1970 From: Salil Mehta Subject: [PATCH net-next 4/9] net: hns3: Fix for phy link issue when using marvell phy driver Date: Sun, 12 Aug 2018 10:47:33 +0100 Message-ID: <20180812094738.14852-5-salil.mehta@huawei.com> References: <20180812094738.14852-1-salil.mehta@huawei.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , , , , , , Jian Shen To: Return-path: In-Reply-To: <20180812094738.14852-1-salil.mehta@huawei.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org From: Jian Shen For marvell phy m88e1510, bit SUPPORTED_FIBRE of phydev->supported is default on. Both phy_resume() and phy_suspend() will check the SUPPORTED_FIBRE bit and write register of fibre page. Currently in hns3 driver, the SUPPORTED_FIBRE bit will be cleared after phy_connect_direct() finished. Because phy_resume() is called in phy_connect_direct(), and phy_suspend() is called when disconnect phy device, so the operation for fibre page register is not symmetrical. It will cause phy link issue when reload hns3 driver. This patch fixes it by disable the SUPPORTED_FIBRE before connecting phy. This is a temporary scheme for DTS2018050311542. I'm contacking with the FAE of marvell phy, wish to get a better way to deal with it. Signed-off-by: Jian Shen Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c index 85a123d40e8b..398971a062f4 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c @@ -202,6 +202,8 @@ int hclge_mac_connect_phy(struct hclge_dev *hdev) if (!phydev) return 0; + phydev->supported &= ~SUPPORTED_FIBRE; + ret = phy_connect_direct(netdev, phydev, hclge_mac_adjust_link, PHY_INTERFACE_MODE_SGMII); -- 2.11.0