From mboxrd@z Thu Jan 1 00:00:00 1970 From: Saeed Mahameed Subject: [net-next 7/8] net/mlx5: Added "per_lane_error_counters" cap bit to PCAM Date: Thu, 18 Oct 2018 13:39:06 -0700 Message-ID: <20181018203907.25149-8-saeedm@mellanox.com> References: <20181018203907.25149-1-saeedm@mellanox.com> Cc: Shay Agroskin , Saeed Mahameed To: "David S. Miller" , netdev@vger.kernel.org Return-path: Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:42016 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727158AbeJSEmQ (ORCPT ); Fri, 19 Oct 2018 00:42:16 -0400 In-Reply-To: <20181018203907.25149-1-saeedm@mellanox.com> Sender: netdev-owner@vger.kernel.org List-ID: From: Shay Agroskin Added "Per lane raw errors" capability bit in Ports Capabilities Mask (PCAM) enhanced features layout. This bit determines if the fields "phy_raw_errors_laneX" in "Physical Layer statistical" counters group are supported. Signed-off-by: Shay Agroskin Reviewed-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- include/linux/mlx5/mlx5_ifc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 47b09a742ae5..dbff9ff28f2c 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -8140,7 +8140,8 @@ struct mlx5_ifc_pcam_enhanced_features_bits { u8 rx_icrc_encapsulated_counter[0x1]; u8 reserved_at_6e[0x8]; u8 pfcc_mask[0x1]; - u8 reserved_at_77[0x4]; + u8 reserved_at_77[0x3]; + u8 per_lane_error_counters[0x1]; u8 rx_buffer_fullness_counters[0x1]; u8 ptys_connector_type[0x1]; u8 reserved_at_7d[0x1]; -- 2.17.2