From mboxrd@z Thu Jan 1 00:00:00 1970 From: Max Uvarov Subject: [PATCH] dp83867: fix speed 10 in sgmii mode Date: Thu, 25 Oct 2018 14:05:30 +0300 Message-ID: <20181025110530.22826-1-muvarov@gmail.com> Cc: andrew@lunn.ch, f.fainelli@gmail.com, netdev@vger.kernel.org, Max Uvarov To: linux-kernel@vger.kernel.org Return-path: Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org For support 10Mps sped in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit of DP83867_10M_SGMII_CFG register has to be cleared by software. That does not affect speeds 100 and 1000 so can be done on init. Signed-off-by: Max Uvarov --- http://www.ti.com/lit/ds/symlink/dp83867e.pdf page 87 for register bits and page 23 last sentance that bit needs to be cleared. drivers/net/phy/dp83867.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index ab58224f897f..1df4da3f70a9 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -37,6 +37,7 @@ #define DP83867_STRAP_STS1 0x006E #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 +#define DP83867_10M_SGMII_CFG 0x016F #define DP83867_SW_RESET BIT(15) #define DP83867_SW_RESTART BIT(14) @@ -79,6 +80,9 @@ /* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) +/* 10M_SGMII_CFG bits */ +#define DP83867_10M_SGMII_RATE_ADAPT BIT(7) + enum { DP83867_PORT_MIRROING_KEEP, DP83867_PORT_MIRROING_EN, @@ -285,6 +289,24 @@ static int dp83867_config_init(struct phy_device *phydev) } } + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* For support SPEED_10 in SGMII mode + * DP83867_10M_SGMII_RATE_ADAPT bit + * has to be cleared by software. That + * does not affect SPEED_100 and + * SPEED_1000. + */ + val = phy_read_mmd(phydev, DP83867_DEVADDR, + DP83867_10M_SGMII_CFG); + val &= ~DP83867_10M_SGMII_RATE_ADAPT; + ret = phy_write_mmd(phydev, DP83867_DEVADDR, + DP83867_10M_SGMII_CFG, val); + if (ret) { + WARN_ONCE(1, "dp83867: error DP83867_10M_SGMII_CFG read\n"); + return ret; + } + } + /* Enable Interrupt output INT_OE in CFG3 register */ if (phy_interrupt_is_valid(phydev)) { val = phy_read(phydev, DP83867_CFG3); -- 2.17.1