From mboxrd@z Thu Jan 1 00:00:00 1970 From: Oleg Subject: maximum number of cpu cores for interrupt handling Date: Thu, 22 Nov 2018 16:21:23 +0300 Message-ID: <20181122132123.GB15537@legohost> Reply-To: Oleg Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit To: netdev@vger.kernel.org Return-path: Received: from forward102j.mail.yandex.net ([5.45.198.243]:41316 "EHLO forward102j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436848AbeKWAIL (ORCPT ); Thu, 22 Nov 2018 19:08:11 -0500 Received: from mxback2j.mail.yandex.net (mxback2j.mail.yandex.net [IPv6:2a02:6b8:0:1619::10b]) by forward102j.mail.yandex.net (Yandex) with ESMTP id E814C1E809E0 for ; Thu, 22 Nov 2018 16:21:29 +0300 (MSK) Content-Disposition: inline Sender: netdev-owner@vger.kernel.org List-ID: Hi, all. I found info that IO APIC limit the number of cpu cores for interrupt handling to 8(because of just 4 bits using for cpu number or something like this). But now MSI/MSI-X is used for interrupts and i don't know is this limit is actual now. For example, i have 4 nic with 8 rx/tx queues each and 32 cpu cores. Can i scale nic interrupt handling to all this cores with smp_affinity? Thanks. -- Олег Неманов (Oleg Nemanov)