From: Andrew Lunn <andrew@lunn.ch>
To: gerg@kernel.org
Cc: sean.wang@mediatek.com, vivien.didelot@savoirfairelinux.com,
f.fainelli@gmail.com, netdev@vger.kernel.org, blogic@openwrt.org,
neil@brown.name
Subject: Re: [PATCH 0/3]: net: dsa: mt7530: support MT7530 in the MT7621 SoC
Date: Fri, 30 Nov 2018 14:33:13 +0100 [thread overview]
Message-ID: <20181130133313.GB11747@lunn.ch> (raw)
In-Reply-To: <20181130075737.8041-1-gerg@kernel.org>
> 2. Maximal sized RX packets get silently dropped. So receive side packets
> that are large (perfect case is the all-but-last packets in a fragemented
> larger packet) appear to be dropped at the mt7621 ethernet MAC level.
> The 7530 MIB switch register counters show receive packets at the physical
> switch port side and at the CPU switch port - but I get no packets
> received or errors in the 7621 ethernet MAC. If I set the mtu of the
> server at the other end a little smaller (a few bytes is enough) then
> I get all the packets through. It seems like the DSA/VLAN tag bytes
> are causing a too large packet to get silently dropped somewhere.
Hi Gerg
Try increasing the MTU on the master device. Some hardware will reject
receiving packets bigger than the MTU. But if you increase the MTU by
the DSA header size, it will then receive the frame.
I have a patchset i will be posting soon to do this automatically.
Andrew
next prev parent reply other threads:[~2018-12-01 0:42 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-30 7:57 [PATCH 0/3]: net: dsa: mt7530: support MT7530 in the MT7621 SoC gerg
2018-11-30 7:57 ` [PATCH 1/3] net: dsa: mt7530: make clock/regulator setup optional gerg
2018-11-30 7:57 ` [PATCH 2/3] net: dsa: mt7530: optional setting CPU field in MFC register gerg
2018-11-30 7:57 ` [PATCH 3/3] dt-bindings: net: dsa: add new bindings MT7530 gerg
2018-11-30 17:41 ` Florian Fainelli
2018-12-03 7:03 ` Greg Ungerer
2018-12-03 13:19 ` Andrew Lunn
2018-11-30 11:27 ` [PATCH 0/3]: net: dsa: mt7530: support MT7530 in the MT7621 SoC René van Dorst
2018-11-30 13:25 ` Greg Ungerer
2018-11-30 11:30 ` René van Dorst
2018-11-30 12:16 ` Bjørn Mork
2018-11-30 13:41 ` Greg Ungerer
2018-11-30 13:42 ` Andrew Lunn
2018-12-03 7:20 ` Greg Ungerer
2018-12-03 11:34 ` Bjørn Mork
2018-12-03 14:00 ` René van Dorst
2018-12-03 14:02 ` John Crispin
2018-12-07 7:12 ` Greg Ungerer
2018-12-04 7:23 ` Greg Ungerer
2018-12-11 5:02 ` NeilBrown
2018-12-11 8:28 ` Bjørn Mork
2018-12-16 22:08 ` NeilBrown
2018-12-16 22:14 ` David Miller
2018-12-16 23:19 ` NeilBrown
2018-12-17 0:00 ` Florian Fainelli
2018-12-17 7:11 ` NeilBrown
2018-11-30 13:33 ` Andrew Lunn [this message]
2018-12-03 6:47 ` Greg Ungerer
2018-11-30 13:37 ` Andrew Lunn
2018-11-30 13:45 ` Greg Ungerer
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