From mboxrd@z Thu Jan 1 00:00:00 1970 From: Antoine Tenart Subject: Re: [PATCH net] net: mvpp2: 10G modes aren't supported on all ports Date: Wed, 12 Dec 2018 10:30:33 +0100 Message-ID: <20181212093033.GA3219@kwain> References: <20181211163228.26130-1-antoine.tenart@bootlin.com> <20181211163635.GG30658@n2100.armlinux.org.uk> <877egg6jbt.fsf@tkos.co.il> <20181211185156.GH30658@n2100.armlinux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Cc: Baruch Siach , Antoine Tenart , davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, maxime.chevallier@bootlin.com, gregory.clement@bootlin.com, miquel.raynal@bootlin.com, nadavh@marvell.com, stefanc@marvell.com, ymarkman@marvell.com, mw@semihalf.com To: Russell King - ARM Linux Return-path: Content-Disposition: inline In-Reply-To: <20181211185156.GH30658@n2100.armlinux.org.uk> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org Hi Russell, Baruch, On Tue, Dec 11, 2018 at 06:51:56PM +0000, Russell King - ARM Linux wrote: > On Tue, Dec 11, 2018 at 07:53:42PM +0200, Baruch Siach wrote: > > That is, something like this, right? > > > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > > index 125ea99418df..04cb0241ca2b 100644 > > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > > @@ -4404,13 +4404,18 @@ static void mvpp2_phylink_validate(struct net_device *dev, > > switch (state->interface) { > > case PHY_INTERFACE_MODE_10GKR: > > case PHY_INTERFACE_MODE_XAUI: > > + if (port->gop_id != 0) > > + goto empty_set; > > + /* Fall-through */ > > case PHY_INTERFACE_MODE_NA: > > - phylink_set(mask, 10000baseCR_Full); > > - phylink_set(mask, 10000baseSR_Full); > > - phylink_set(mask, 10000baseLR_Full); > > - phylink_set(mask, 10000baseLRM_Full); > > - phylink_set(mask, 10000baseER_Full); > > - phylink_set(mask, 10000baseKR_Full); > > + if (port->gop_id == 0) { > > + phylink_set(mask, 10000baseCR_Full); > > + phylink_set(mask, 10000baseSR_Full); > > + phylink_set(mask, 10000baseLR_Full); > > + phylink_set(mask, 10000baseLRM_Full); > > + phylink_set(mask, 10000baseER_Full); > > + phylink_set(mask, 10000baseKR_Full); > > + } > > /* Fall-through */ > > case PHY_INTERFACE_MODE_RGMII: > > case PHY_INTERFACE_MODE_RGMII_ID: > > > > Yep, looks fine to me, thanks. This looks good, thanks! I'll send a v2. Antoine -- Antoine Ténart, Bootlin Embedded Linux and Kernel engineering https://bootlin.com