* [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers
@ 2018-12-18 19:06 Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 1/7] ethtool: dsa: add pretty dump Vivien Didelot
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch series adds support to pretty dump the registers of user
ports created by the kernel "dsa" subsystem.
The first patch adds the base support for "dsa" interfaces.
The second patch adds the boilerplate for the "mv88e6xxx" DSA driver,
all using 32 registers of 16 bits, the switch ID being assigned
by the kernel driver into the regs version. Support for other DSA
drivers such as "b53" or "ksz" can be added similarly later. Because
the different switches supported by mv88e6xxx have slightly different
register layout, we keep it simple and stupid by providing one dump
function per switch.
The remaining patches add support for the switch models currently
supported by the mv88e6xxx driver. Here's an example of dump of the
32 registers of a 88E6352 port:
# ethtool -d lan3
88E6352 Switch Port Registers
------------------------------
00: Port Status 0x500f
Pause Enabled 0
My Pause 1
802.3 PHY Detected 1
Link Status Down
Duplex Half
Speed 10 Mbps
EEE Enabled 0
Transmitter Paused 0
Flow Control 0
Config Mode 0xf
01: Physical Control 0x0003
RGMII Receive Timing Control Default
RGMII Transmit Timing Control Default
200 BASE Mode 100
Flow Control's Forced value 0
Force Flow Control 0
Link's Forced value Down
Force Link 0
Duplex's Forced value Half
Force Duplex 0
Force Speed Not forced
02: Jamming Control 0x0000
03: Switch Identifier 0x3521
04: Port Control 0x0433
Source Address Filtering controls Disabled
Egress Mode Unmodified
Ingress & Egress Header Mode 0
IGMP and MLD Snooping 1
Frame Mode Normal
VLAN Tunnel 0
TagIfBoth 0
Initial Priority assignment Tag & IP Priority
Egress Flooding mode No unknown DA
Port State Forwarding
05: Port Control 1 0x0000
Message Port 0
Trunk Port 0
Trunk ID 0
FID[11:4] 0x000
06: Port Base VLAN Map (Header) 0x0060
FID[3:0] 0x000
VLANTable 5 6
07: Default VLAN ID & Priority 0x0000
Default Priority 0x0
Force to use Default VID 0
Default VLAN Identifier 0
08: Port Control 2 0x2080
Force good FCS in the frame 0
Jumbo Mode 10240
802.1QMode Disabled
Discard Tagged Frames 0
Discard Untagged Frames 0
Map using DA hits 1
ARP Mirror enable 0
Egress Monitor Source Port 0
Ingress Monitor Source Port 0
Use Default Queue Priority 0
Default Queue Priority 0x0
09: Egress Rate Control 0x0001
10: Egress Rate Control 2 0x0000
11: Port Association Vector 0x0001
12: Port ATU Control 0x0000
13: Override 0x0000
14: Policy Control 0x0000
15: Port Ether Type 0x9100
16: InDiscardsLo Frame Counter 0x0000
17: InDiscardsHi Frame Counter 0x0000
18: InFiltered/TcamCtr Frame Counter 0x0000
19: Rx Frame Counter 0x0000
20: Reserved 0x0000
21: Reserved 0x0000
22: LED Control 0x0022
23: Reserved 0x0000
24: Tag Remap 0-3 0x3210
25: Tag Remap 4-7 0x7654
26: Reserved 0x0000
27: Queue Counters 0x8000
28: Reserved 0x0000
29: Reserved 0x0000
30: Reserved 0x0000
31: Reserved 0x0000
Changes in v2:
- read the switch model from regs->version instead of regs[3]
Vivien Didelot (7):
ethtool: dsa: add pretty dump
ethtool: dsa: mv88e6xxx: add pretty dump
ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185
ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161
ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352
ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390
ethtool: dsa: mv88e6xxx: add pretty dump for others
Makefile.am | 2 +-
dsa.c | 685 ++++++++++++++++++++++++++++++++++++++++++++++++++++
ethtool.c | 1 +
internal.h | 3 +
4 files changed, 690 insertions(+), 1 deletion(-)
create mode 100644 dsa.c
--
2.20.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/7] ethtool: dsa: add pretty dump
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 2/7] ethtool: dsa: mv88e6xxx: " Vivien Didelot
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds the preliminary bits for pretty dumping the registers
of the "dsa" kernel drivers.
This patch does not pretty dump anything yet.
Following patches will add support for the "mv88e6xxx" DSA driver.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
Makefile.am | 2 +-
dsa.c | 12 ++++++++++++
ethtool.c | 1 +
internal.h | 3 +++
4 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 dsa.c
diff --git a/Makefile.am b/Makefile.am
index 14f79b6..468eed1 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -9,7 +9,7 @@ ethtool_SOURCES = ethtool.c ethtool-copy.h internal.h net_tstamp-copy.h \
rxclass.c
if ETHTOOL_ENABLE_PRETTY_DUMP
ethtool_SOURCES += \
- amd8111e.c de2104x.c e100.c e1000.c et131x.c igb.c \
+ amd8111e.c de2104x.c dsa.c e100.c e1000.c et131x.c igb.c \
fec_8xx.c ibm_emac.c ixgb.c ixgbe.c natsemi.c \
pcnet32.c realtek.c tg3.c marvell.c vioc.c \
smsc911x.c at76c50x-usb.c sfc.c stmmac.c \
diff --git a/dsa.c b/dsa.c
new file mode 100644
index 0000000..83396b5
--- /dev/null
+++ b/dsa.c
@@ -0,0 +1,12 @@
+#include <stdio.h>
+#include <string.h>
+
+#include "internal.h"
+
+int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
+{
+ /* DSA per-driver register dump */
+
+ /* Fallback to hexdump */
+ return 1;
+}
diff --git a/ethtool.c b/ethtool.c
index 2f7e96b..f1f1ec2 100644
--- a/ethtool.c
+++ b/ethtool.c
@@ -1166,6 +1166,7 @@ static const struct {
{ "vmxnet3", vmxnet3_dump_regs },
{ "fjes", fjes_dump_regs },
{ "lan78xx", lan78xx_dump_regs },
+ { "dsa", dsa_dump_regs },
#endif
};
diff --git a/internal.h b/internal.h
index b239dc7..84b0f9c 100644
--- a/internal.h
+++ b/internal.h
@@ -354,4 +354,7 @@ int fjes_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs);
/* MICROCHIP LAN78XX USB ETHERNET Controller */
int lan78xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs);
+/* Distributed Switch Architecture */
+int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs);
+
#endif /* ETHTOOL_INTERNAL_H__ */
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/7] ethtool: dsa: mv88e6xxx: add pretty dump
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 1/7] ethtool: dsa: add pretty dump Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 3/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185 Vivien Didelot
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
The mv88e6xxx DSA driver supports many Marvell devices all using 32
registers of 16 bits. However each devices have a slightly different
register definition.
This patch adds the boilerplate for providing an optional function
per mv88e6xxx switch. It does not pretty dump anything yet.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/dsa.c b/dsa.c
index 83396b5..5de60b2 100644
--- a/dsa.c
+++ b/dsa.c
@@ -3,9 +3,86 @@
#include "internal.h"
+/* Macros and dump functions for the 16-bit mv88e6xxx per-port registers */
+
+#define REG(_reg, _name, _val) \
+ printf("%.02u: %-38.38s 0x%.4x\n", _reg, _name, _val)
+
+#define FIELD(_name, _fmt, ...) \
+ printf(" %-36.36s " _fmt "\n", _name, ##__VA_ARGS__)
+
+#define FIELD_BITMAP(_name, _val) \
+ FIELD(_name, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", \
+ ((_val) & 0x0001) ? "0 " : "", \
+ ((_val) & 0x0002) ? "1 " : "", \
+ ((_val) & 0x0004) ? "2 " : "", \
+ ((_val) & 0x0008) ? "3 " : "", \
+ ((_val) & 0x0010) ? "4 " : "", \
+ ((_val) & 0x0020) ? "5 " : "", \
+ ((_val) & 0x0040) ? "6 " : "", \
+ ((_val) & 0x0080) ? "7 " : "", \
+ ((_val) & 0x0100) ? "8 " : "", \
+ ((_val) & 0x0200) ? "9 " : "", \
+ ((_val) & 0x0400) ? "10 " : "", \
+ ((_val) & 0x0800) ? "11 " : "", \
+ ((_val) & 0x1000) ? "12 " : "", \
+ ((_val) & 0x2000) ? "13 " : "", \
+ ((_val) & 0x4000) ? "14 " : "", \
+ ((_val) & 0x8000) ? "15 " : "")
+
+struct dsa_mv88e6xxx_switch {
+ void (*dump)(int reg, u16 val);
+ const char *name;
+ u16 id;
+};
+
+static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
+};
+
+static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs)
+{
+ const struct dsa_mv88e6xxx_switch *sw = NULL;
+ const u16 *data = (u16 *)regs->data;
+ u16 id;
+ int i;
+
+ /* Marvell chips have 32 per-port 16-bit registers */
+ if (regs->len < 32 * 2)
+ return 1;
+
+ id = regs->version & 0xfff0;
+
+ for (i = 0; i < ARRAY_SIZE(dsa_mv88e6xxx_switches); i++) {
+ if (id == dsa_mv88e6xxx_switches[i].id) {
+ sw = &dsa_mv88e6xxx_switches[i];
+ break;
+ }
+ }
+
+ if (!sw)
+ return 1;
+
+ printf("%s Switch Port Registers\n", sw->name);
+ printf("------------------------------\n");
+
+ for (i = 0; i < 32; i++)
+ if (sw->dump)
+ sw->dump(i, data[i]);
+ else
+ REG(i, "", data[i]);
+
+ return 0;
+}
+
+#undef FIELD_BITMAP
+#undef FIELD
+#undef REG
+
int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
{
/* DSA per-driver register dump */
+ if (!dsa_mv88e6xxx_dump_regs(regs))
+ return 0;
/* Fallback to hexdump */
return 1;
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 1/7] ethtool: dsa: add pretty dump Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 2/7] ethtool: dsa: mv88e6xxx: " Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161 Vivien Didelot
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds support for pretty dump the port registers of the
88E6185 switch.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/dsa.c b/dsa.c
index 5de60b2..c7e3dd1 100644
--- a/dsa.c
+++ b/dsa.c
@@ -30,6 +30,66 @@
((_val) & 0x4000) ? "14 " : "", \
((_val) & 0x8000) ? "15 " : "")
+static void dsa_mv88e6185(int reg, u16 val)
+{
+ switch (reg) {
+ case 0:
+ REG(reg, "Port Status", val);
+ break;
+ case 1:
+ REG(reg, "PCS Control", val);
+ break;
+ case 3:
+ REG(reg, "Switch Identifier", val);
+ break;
+ case 4:
+ REG(reg, "Port Control", val);
+ break;
+ case 5:
+ REG(reg, "Port Control 1", val);
+ break;
+ case 6:
+ REG(reg, "Port Base VLAN Map (Header)", val);
+ break;
+ case 7:
+ REG(reg, "Default VLAN ID & Priority", val);
+ break;
+ case 8:
+ REG(reg, "Port Control 2", val);
+ break;
+ case 9:
+ REG(reg, "Rate Control", val);
+ break;
+ case 10:
+ REG(reg, "Rate Control 2", val);
+ break;
+ case 11:
+ REG(reg, "Port Association Vector", val);
+ break;
+ case 16:
+ REG(reg, "InDiscardsLo Frame Counter", val);
+ break;
+ case 17:
+ REG(reg, "InDiscardsHi Frame Counter", val);
+ break;
+ case 18:
+ REG(reg, "InFiltered Frame Counter", val);
+ break;
+ case 19:
+ REG(reg, "OutFiltered Frame Counter", val);
+ break;
+ case 24:
+ REG(reg, "Tag Remap 0-3", val);
+ break;
+ case 25:
+ REG(reg, "Tag Remap 4-7", val);
+ break;
+ default:
+ REG(reg, "Reserved", val);
+ break;
+ }
+};
+
struct dsa_mv88e6xxx_switch {
void (*dump)(int reg, u16 val);
const char *name;
@@ -37,6 +97,7 @@ struct dsa_mv88e6xxx_switch {
};
static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
+ { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
};
static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs)
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (2 preceding siblings ...)
2018-12-18 19:06 ` [PATCH v2 3/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185 Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 5/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352 Vivien Didelot
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds support for pretty dump the port registers of the
88E6161 and 88E6123 switches, which both share the same datasheet.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/dsa.c b/dsa.c
index c7e3dd1..ab21d01 100644
--- a/dsa.c
+++ b/dsa.c
@@ -30,6 +30,168 @@
((_val) & 0x4000) ? "14 " : "", \
((_val) & 0x8000) ? "15 " : "")
+static void dsa_mv88e6161(int reg, u16 val)
+{
+ switch (reg) {
+ case 0:
+ REG(reg, "Port Status", val);
+ FIELD("Pause Enabled", "%u", !!(val & 0x8000));
+ FIELD("My Pause", "%u", !!(val & 0x4000));
+ FIELD("Half-duplex Flow Control", "%u", !!(val & 0x2000));
+ FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
+ FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
+ FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
+ FIELD("Speed", "%s",
+ (val & 0x0300) == 0x0000 ? "10 Mbps" :
+ (val & 0x0300) == 0x0100 ? "100 Mbps" :
+ (val & 0x0300) == 0x0200 ? "1000 Mbps" :
+ (val & 0x0300) == 0x0300 ? "Reserved" : "?");
+ FIELD("Auto-Media Detect Disable", "%u", !!(val & 0x0040));
+ FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
+ FIELD("Flow Control", "%u", !!(val & 0x0010));
+ FIELD("Config Duplex", "%s", val & 0x0008 ? "Full" : "Half");
+ FIELD("Config Mode", "0x%x", val & 0x0007);
+ break;
+ case 1:
+ REG(reg, "PCS Control", val);
+ FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080));
+ FIELD("Force Flow Control", "%u", !!(val & 0x0040));
+ FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
+ FIELD("Force Link", "%u", !!(val & 0x0010));
+ FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
+ FIELD("Force Duplex", "%u", !!(val & 0x0004));
+ FIELD("Force Speed", "%s",
+ (val & 0x0003) == 0x0000 ? "10 Mbps" :
+ (val & 0x0003) == 0x0001 ? "100 Mbps" :
+ (val & 0x0003) == 0x0002 ? "1000 Mbps" :
+ (val & 0x0003) == 0x0003 ? "Not forced" : "?");
+ break;
+ case 2:
+ REG(reg, "Jamming Control", val);
+ break;
+ case 3:
+ REG(reg, "Switch Identifier", val);
+ break;
+ case 4:
+ REG(reg, "Port Control", val);
+ FIELD("Source Address Filtering controls", "%s",
+ (val & 0xc000) == 0x0000 ? "Disabled" :
+ (val & 0xc000) == 0x4000 ? "Drop On Lock" :
+ (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
+ (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
+ FIELD("Egress Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "Unmodified" :
+ (val & 0x3000) == 0x1000 ? "Untagged" :
+ (val & 0x3000) == 0x2000 ? "Tagged" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
+ FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
+ FIELD("Frame Mode", "%s",
+ (val & 0x0300) == 0x0000 ? "Normal" :
+ (val & 0x0300) == 0x0100 ? "DSA" :
+ (val & 0x0300) == 0x0200 ? "Provider" :
+ (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
+ FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
+ FIELD("TagIfBoth", "%u", !!(val & 0x0040));
+ FIELD("Initial Priority assignment", "%s",
+ (val & 0x0030) == 0x0000 ? "Defaults" :
+ (val & 0x0030) == 0x0010 ? "Tag Priority" :
+ (val & 0x0030) == 0x0020 ? "IP Priority" :
+ (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
+ FIELD("Egress Flooding mode", "%s",
+ (val & 0x000c) == 0x0000 ? "No unknown DA" :
+ (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
+ (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
+ (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
+ FIELD("Port State", "%s",
+ (val & 0x0003) == 0x0000 ? "Disabled" :
+ (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
+ (val & 0x0003) == 0x0002 ? "Learning" :
+ (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
+ break;
+ case 5:
+ REG(reg, "Port Control 1", val);
+ FIELD("Message Port", "%u", !!(val & 0x8000));
+ FIELD("Trunk Port", "%u", !!(val & 0x4000));
+ FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8);
+ FIELD("FID[5:4]", "0x%.2x", (val & 0x0003) << 4);
+ break;
+ case 6:
+ REG(reg, "Port Base VLAN Map (Header)", val);
+ FIELD("FID[3:0]", "0x%.2x", (val & 0xf000) >> 12);
+ FIELD_BITMAP("VLANTable", val & 0x003f);
+ break;
+ case 7:
+ REG(reg, "Default VLAN ID & Priority", val);
+ FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
+ FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
+ FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
+ break;
+ case 8:
+ REG(reg, "Port Control 2", val);
+ FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
+ FIELD("Jumbo Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "1522" :
+ (val & 0x3000) == 0x1000 ? "2048" :
+ (val & 0x3000) == 0x2000 ? "10240" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("802.1QMode", "%s",
+ (val & 0x0c00) == 0x0000 ? "Disabled" :
+ (val & 0x0c00) == 0x0400 ? "Fallback" :
+ (val & 0x0c00) == 0x0800 ? "Check" :
+ (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
+ FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
+ FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
+ FIELD("Map using DA hits", "%u", !!(val & 0x0080));
+ FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
+ FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
+ FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
+ break;
+ case 9:
+ REG(reg, "Egress Rate Control", val);
+ break;
+ case 10:
+ REG(reg, "Egress Rate Control 2", val);
+ break;
+ case 11:
+ REG(reg, "Port Association Vector", val);
+ break;
+ case 12:
+ REG(reg, "Port ATU Control", val);
+ break;
+ case 13:
+ REG(reg, "Priority Override", val);
+ break;
+ case 15:
+ REG(reg, "PortEType", val);
+ break;
+ case 16:
+ REG(reg, "InDiscardsLo Frame Counter", val);
+ break;
+ case 17:
+ REG(reg, "InDiscardsHi Frame Counter", val);
+ break;
+ case 18:
+ REG(reg, "InFiltered Frame Counter", val);
+ break;
+ case 19:
+ REG(reg, "OutFiltered Frame Counter", val);
+ break;
+ case 24:
+ REG(reg, "Tag Remap 0-3", val);
+ break;
+ case 25:
+ REG(reg, "Tag Remap 4-7", val);
+ break;
+ case 27:
+ REG(reg, "Queue Counters", val);
+ break;
+ default:
+ REG(reg, "Reserved", val);
+ break;
+ }
+}
+
static void dsa_mv88e6185(int reg, u16 val)
{
switch (reg) {
@@ -97,6 +259,8 @@ struct dsa_mv88e6xxx_switch {
};
static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
+ { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 },
+ { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 },
{ .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
};
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (3 preceding siblings ...)
2018-12-18 19:06 ` [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161 Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 6/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390 Vivien Didelot
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds support for pretty dump the port registers of the
88E6172, 88E6176, 88E6240 and 88E6352 switches, which all share the
same datasheet.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/dsa.c b/dsa.c
index ab21d01..09a48c6 100644
--- a/dsa.c
+++ b/dsa.c
@@ -252,6 +252,177 @@ static void dsa_mv88e6185(int reg, u16 val)
}
};
+static void dsa_mv88e6352(int reg, u16 val)
+{
+ switch (reg) {
+ case 0:
+ REG(reg, "Port Status", val);
+ FIELD("Pause Enabled", "%u", !!(val & 0x8000));
+ FIELD("My Pause", "%u", !!(val & 0x4000));
+ FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
+ FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
+ FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
+ FIELD("Speed", "%s",
+ (val & 0x0300) == 0x0000 ? "10 Mbps" :
+ (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" :
+ (val & 0x0300) == 0x0200 ? "1000 Mbps" :
+ (val & 0x0300) == 0x0300 ? "Reserved" : "?");
+ FIELD("EEE Enabled", "%u", !!(val & 0x0040));
+ FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
+ FIELD("Flow Control", "%u", !!(val & 0x0010));
+ FIELD("Config Mode", "0x%x", val & 0x000f);
+ break;
+ case 1:
+ REG(reg, "Physical Control", val);
+ FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default");
+ FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default");
+ FIELD("200 BASE Mode", "%s", val & 0x1000 ? "200" : "100");
+ FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080));
+ FIELD("Force Flow Control", "%u", !!(val & 0x0040));
+ FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
+ FIELD("Force Link", "%u", !!(val & 0x0010));
+ FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
+ FIELD("Force Duplex", "%u", !!(val & 0x0004));
+ FIELD("Force Speed", "%s",
+ (val & 0x0003) == 0x0000 ? "10 Mbps" :
+ (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" :
+ (val & 0x0003) == 0x0002 ? "1000 Mbps" :
+ (val & 0x0003) == 0x0003 ? "Not forced" : "?");
+ break;
+ case 2:
+ REG(reg, "Jamming Control", val);
+ break;
+ case 3:
+ REG(reg, "Switch Identifier", val);
+ break;
+ case 4:
+ REG(reg, "Port Control", val);
+ FIELD("Source Address Filtering controls", "%s",
+ (val & 0xc000) == 0x0000 ? "Disabled" :
+ (val & 0xc000) == 0x4000 ? "Drop On Lock" :
+ (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
+ (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
+ FIELD("Egress Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "Unmodified" :
+ (val & 0x3000) == 0x1000 ? "Untagged" :
+ (val & 0x3000) == 0x2000 ? "Tagged" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
+ FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
+ FIELD("Frame Mode", "%s",
+ (val & 0x0300) == 0x0000 ? "Normal" :
+ (val & 0x0300) == 0x0100 ? "DSA" :
+ (val & 0x0300) == 0x0200 ? "Provider" :
+ (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
+ FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
+ FIELD("TagIfBoth", "%u", !!(val & 0x0040));
+ FIELD("Initial Priority assignment", "%s",
+ (val & 0x0030) == 0x0000 ? "Defaults" :
+ (val & 0x0030) == 0x0010 ? "Tag Priority" :
+ (val & 0x0030) == 0x0020 ? "IP Priority" :
+ (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
+ FIELD("Egress Flooding mode", "%s",
+ (val & 0x000c) == 0x0000 ? "No unknown DA" :
+ (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
+ (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
+ (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
+ FIELD("Port State", "%s",
+ (val & 0x0003) == 0x0000 ? "Disabled" :
+ (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
+ (val & 0x0003) == 0x0002 ? "Learning" :
+ (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
+ break;
+ case 5:
+ REG(reg, "Port Control 1", val);
+ FIELD("Message Port", "%u", !!(val & 0x8000));
+ FIELD("Trunk Port", "%u", !!(val & 0x4000));
+ FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8);
+ FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4);
+ break;
+ case 6:
+ REG(reg, "Port Base VLAN Map (Header)", val);
+ FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12);
+ FIELD_BITMAP("VLANTable", val & 0x007f);
+ break;
+ case 7:
+ REG(reg, "Default VLAN ID & Priority", val);
+ FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
+ FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
+ FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
+ break;
+ case 8:
+ REG(reg, "Port Control 2", val);
+ FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
+ FIELD("Jumbo Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "1522" :
+ (val & 0x3000) == 0x1000 ? "2048" :
+ (val & 0x3000) == 0x2000 ? "10240" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("802.1QMode", "%s",
+ (val & 0x0c00) == 0x0000 ? "Disabled" :
+ (val & 0x0c00) == 0x0400 ? "Fallback" :
+ (val & 0x0c00) == 0x0800 ? "Check" :
+ (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
+ FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
+ FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
+ FIELD("Map using DA hits", "%u", !!(val & 0x0080));
+ FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
+ FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
+ FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
+ FIELD("Use Default Queue Priority", "%u", !!(val & 0x0008));
+ FIELD("Default Queue Priority", "0x%x", (val & 0x0006) >> 1);
+ break;
+ case 9:
+ REG(reg, "Egress Rate Control", val);
+ break;
+ case 10:
+ REG(reg, "Egress Rate Control 2", val);
+ break;
+ case 11:
+ REG(reg, "Port Association Vector", val);
+ break;
+ case 12:
+ REG(reg, "Port ATU Control", val);
+ break;
+ case 13:
+ REG(reg, "Override", val);
+ break;
+ case 14:
+ REG(reg, "Policy Control", val);
+ break;
+ case 15:
+ REG(reg, "Port Ether Type", val);
+ break;
+ case 16:
+ REG(reg, "InDiscardsLo Frame Counter", val);
+ break;
+ case 17:
+ REG(reg, "InDiscardsHi Frame Counter", val);
+ break;
+ case 18:
+ REG(reg, "InFiltered/TcamCtr Frame Counter", val);
+ break;
+ case 19:
+ REG(reg, "Rx Frame Counter", val);
+ break;
+ case 22:
+ REG(reg, "LED Control", val);
+ break;
+ case 24:
+ REG(reg, "Tag Remap 0-3", val);
+ break;
+ case 25:
+ REG(reg, "Tag Remap 4-7", val);
+ break;
+ case 27:
+ REG(reg, "Queue Counters", val);
+ break;
+ default:
+ REG(reg, "Reserved", val);
+ break;
+ }
+};
+
struct dsa_mv88e6xxx_switch {
void (*dump)(int reg, u16 val);
const char *name;
@@ -261,7 +432,11 @@ struct dsa_mv88e6xxx_switch {
static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
{ .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 },
{ .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 },
+ { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 },
+ { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 },
{ .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
+ { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 },
+ { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 },
};
static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs)
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 6/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (4 preceding siblings ...)
2018-12-18 19:06 ` [PATCH v2 5/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352 Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 7/7] ethtool: dsa: mv88e6xxx: add pretty dump for others Vivien Didelot
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds support for pretty dump the port registers of the
88E6190, 88E6290, 88E6390, 88E6190X and 88E6390X switches, which all
share the same datasheet.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/dsa.c b/dsa.c
index 09a48c6..9f50927 100644
--- a/dsa.c
+++ b/dsa.c
@@ -423,6 +423,183 @@ static void dsa_mv88e6352(int reg, u16 val)
}
};
+static void dsa_mv88e6390(int reg, u16 val)
+{
+ switch (reg) {
+ case 0:
+ REG(reg, "Port Status", val);
+ FIELD("Transmit Pause Enable bit", "%u", !!(val & 0x8000));
+ FIELD("Receive Pause Enable bit", "%u", !!(val & 0x4000));
+ FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
+ FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
+ FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
+ FIELD("Speed", "%s",
+ (val & 0x0300) == 0x0000 ? "10 Mbps" :
+ (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" :
+ (val & 0x0300) == 0x0200 ? "1000 Mbps" :
+ (val & 0x0300) == 0x0300 ? "10 Gb or 2500 Mbps" : "?");
+ FIELD("Duplex Fixed", "%u", !!(val & 0x0080));
+ FIELD("EEE Enabled", "%u", !!(val & 0x0040));
+ FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
+ FIELD("Flow Control", "%u", !!(val & 0x0010));
+ FIELD("Config Mode", "0x%x", val & 0x000f);
+ break;
+ case 1:
+ REG(reg, "Physical Control", val);
+ FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default");
+ FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default");
+ FIELD("Force Speed", "%u", !!(val & 0x2000));
+ FIELD("Alternate Speed Mode", "%s", val & 0x1000 ? "Alternate" : "Normal");
+ FIELD("MII PHY Mode", "%s", val & 0x0800 ? "PHY" : "MAC");
+ FIELD("EEE force value", "%u", !!(val & 0x0200));
+ FIELD("Force EEE", "%u", !!(val & 0x0100));
+ FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
+ FIELD("Force Link", "%u", !!(val & 0x0010));
+ FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
+ FIELD("Force Duplex", "%u", !!(val & 0x0004));
+ FIELD("Force Speed", "%s",
+ (val & 0x0003) == 0x0000 ? "10 Mbps" :
+ (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" :
+ (val & 0x0003) == 0x0002 ? "1000 Mbps" :
+ (val & 0x0003) == 0x0003 ? "10 Gb or 2500 Mbps" : "?");
+ break;
+ case 2:
+ REG(reg, "Flow Control", val);
+ break;
+ case 3:
+ REG(reg, "Switch Identifier", val);
+ break;
+ case 4:
+ REG(reg, "Port Control", val);
+ FIELD("Source Address Filtering controls", "%s",
+ (val & 0xc000) == 0x0000 ? "Disabled" :
+ (val & 0xc000) == 0x4000 ? "Drop On Lock" :
+ (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
+ (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
+ FIELD("Egress Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "Unmodified" :
+ (val & 0x3000) == 0x1000 ? "Untagged" :
+ (val & 0x3000) == 0x2000 ? "Tagged" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
+ FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
+ FIELD("Frame Mode", "%s",
+ (val & 0x0300) == 0x0000 ? "Normal" :
+ (val & 0x0300) == 0x0100 ? "DSA" :
+ (val & 0x0300) == 0x0200 ? "Provider" :
+ (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
+ FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
+ FIELD("TagIfBoth", "%u", !!(val & 0x0040));
+ FIELD("Initial Priority assignment", "%s",
+ (val & 0x0030) == 0x0000 ? "Defaults" :
+ (val & 0x0030) == 0x0010 ? "Tag Priority" :
+ (val & 0x0030) == 0x0020 ? "IP Priority" :
+ (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
+ FIELD("Egress Flooding mode", "%s",
+ (val & 0x000c) == 0x0000 ? "No unknown DA" :
+ (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
+ (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
+ (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
+ FIELD("Port State", "%s",
+ (val & 0x0003) == 0x0000 ? "Disabled" :
+ (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
+ (val & 0x0003) == 0x0002 ? "Learning" :
+ (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
+ break;
+ case 5:
+ REG(reg, "Port Control 1", val);
+ FIELD("Message Port", "%u", !!(val & 0x8000));
+ FIELD("LAG Port", "%u", !!(val & 0x4000));
+ FIELD("VTU Page", "%u", !!(val & 0x2000));
+ FIELD("LAG ID", "%u", (val & 0x0f00) >> 8);
+ FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4);
+ break;
+ case 6:
+ REG(reg, "Port Base VLAN Map (Header)", val);
+ FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12);
+ FIELD("Force Mapping", "%u", !!(val & 0x0800));
+ FIELD_BITMAP("VLANTable", val & 0x007ff);
+ break;
+ case 7:
+ REG(reg, "Default VLAN ID & Priority", val);
+ FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
+ FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
+ FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
+ break;
+ case 8:
+ REG(reg, "Port Control 2", val);
+ FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
+ FIELD("Allow bad FCS", "%u", !!(val & 0x4000));
+ FIELD("Jumbo Mode", "%s",
+ (val & 0x3000) == 0x0000 ? "1522" :
+ (val & 0x3000) == 0x1000 ? "2048" :
+ (val & 0x3000) == 0x2000 ? "10240" :
+ (val & 0x3000) == 0x3000 ? "Reserved" : "?");
+ FIELD("802.1QMode", "%s",
+ (val & 0x0c00) == 0x0000 ? "Disabled" :
+ (val & 0x0c00) == 0x0400 ? "Fallback" :
+ (val & 0x0c00) == 0x0800 ? "Check" :
+ (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
+ FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
+ FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
+ FIELD("Map using DA hits", "%u", !!(val & 0x0080));
+ FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
+ FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
+ FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
+ FIELD("Allow VID of Zero", "%u", !!(val & 0x0008));
+ FIELD("Default Queue Priority", "0x%x", val & 0x0007);
+ break;
+ case 9:
+ REG(reg, "Egress Rate Control", val);
+ break;
+ case 10:
+ REG(reg, "Egress Rate Control 2", val);
+ break;
+ case 11:
+ REG(reg, "Port Association Vector", val);
+ break;
+ case 12:
+ REG(reg, "Port ATU Control", val);
+ break;
+ case 13:
+ REG(reg, "Override", val);
+ break;
+ case 14:
+ REG(reg, "Policy Control", val);
+ break;
+ case 15:
+ REG(reg, "Port Ether Type", val);
+ break;
+ case 22:
+ REG(reg, "LED Control", val);
+ break;
+ case 23:
+ REG(reg, "IP Priority Mapping Table", val);
+ break;
+ case 24:
+ REG(reg, "IEEE Priority Mapping Table", val);
+ break;
+ case 25:
+ REG(reg, "Port Control 3", val);
+ break;
+ case 27:
+ REG(reg, "Queue Counters", val);
+ break;
+ case 28:
+ REG(reg, "Queue Control", val);
+ break;
+ case 30:
+ REG(reg, "Cut Through Control", val);
+ break;
+ case 31:
+ REG(reg, "Debug Counters", val);
+ break;
+ default:
+ REG(reg, "Reserved", val);
+ break;
+ }
+};
+
struct dsa_mv88e6xxx_switch {
void (*dump)(int reg, u16 val);
const char *name;
@@ -430,13 +607,18 @@ struct dsa_mv88e6xxx_switch {
};
static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
+ { .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 },
+ { .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 },
{ .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 },
{ .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 },
{ .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 },
{ .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 },
+ { .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 },
{ .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
{ .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 },
+ { .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 },
{ .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 },
+ { .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 },
};
static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs)
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 7/7] ethtool: dsa: mv88e6xxx: add pretty dump for others
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (5 preceding siblings ...)
2018-12-18 19:06 ` [PATCH v2 6/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390 Vivien Didelot
@ 2018-12-18 19:06 ` Vivien Didelot
2018-12-19 9:41 ` [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Andrew Lunn
2019-01-18 18:40 ` John W. Linville
8 siblings, 0 replies; 10+ messages in thread
From: Vivien Didelot @ 2018-12-18 19:06 UTC (permalink / raw)
To: netdev; +Cc: Chris Healy, Vivien Didelot, John W . Linville, f.fainelli,
andrew
This patch adds basic pretty dump for the remaining mv88e6xxx switches
supported by the kernel DSA driver.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
---
dsa.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/dsa.c b/dsa.c
index 9f50927..02a10dd 100644
--- a/dsa.c
+++ b/dsa.c
@@ -607,17 +607,31 @@ struct dsa_mv88e6xxx_switch {
};
static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
+ { .id = 0x04a0, .name = "88E6085 ", .dump = NULL },
+ { .id = 0x0950, .name = "88E6095 ", .dump = NULL },
+ { .id = 0x0990, .name = "88E6097 ", .dump = NULL },
{ .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 },
{ .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 },
+ { .id = 0x1060, .name = "88E6131 ", .dump = NULL },
+ { .id = 0x1150, .name = "88E6320 ", .dump = NULL },
{ .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 },
{ .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 },
+ { .id = 0x1650, .name = "88E6165 ", .dump = NULL },
+ { .id = 0x1710, .name = "88E6171 ", .dump = NULL },
{ .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 },
+ { .id = 0x1750, .name = "88E6175 ", .dump = NULL },
{ .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 },
{ .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 },
+ { .id = 0x1910, .name = "88E6191 ", .dump = NULL },
{ .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
{ .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 },
{ .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 },
+ { .id = 0x3100, .name = "88E6321 ", .dump = NULL },
+ { .id = 0x3400, .name = "88E6141 ", .dump = NULL },
+ { .id = 0x3410, .name = "88E6341 ", .dump = NULL },
{ .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 },
+ { .id = 0x3710, .name = "88E6350 ", .dump = NULL },
+ { .id = 0x3750, .name = "88E6351 ", .dump = NULL },
{ .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 },
};
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (6 preceding siblings ...)
2018-12-18 19:06 ` [PATCH v2 7/7] ethtool: dsa: mv88e6xxx: add pretty dump for others Vivien Didelot
@ 2018-12-19 9:41 ` Andrew Lunn
2019-01-18 18:40 ` John W. Linville
8 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2018-12-19 9:41 UTC (permalink / raw)
To: Vivien Didelot; +Cc: netdev, Chris Healy, John W . Linville, f.fainelli
On Tue, Dec 18, 2018 at 02:06:34PM -0500, Vivien Didelot wrote:
> This patch series adds support to pretty dump the registers of user
> ports created by the kernel "dsa" subsystem.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers
2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
` (7 preceding siblings ...)
2018-12-19 9:41 ` [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Andrew Lunn
@ 2019-01-18 18:40 ` John W. Linville
8 siblings, 0 replies; 10+ messages in thread
From: John W. Linville @ 2019-01-18 18:40 UTC (permalink / raw)
To: Vivien Didelot; +Cc: netdev, Chris Healy, f.fainelli, andrew
On Tue, Dec 18, 2018 at 02:06:34PM -0500, Vivien Didelot wrote:
> This patch series adds support to pretty dump the registers of user
> ports created by the kernel "dsa" subsystem.
>
> The first patch adds the base support for "dsa" interfaces.
>
> The second patch adds the boilerplate for the "mv88e6xxx" DSA driver,
> all using 32 registers of 16 bits, the switch ID being assigned
> by the kernel driver into the regs version. Support for other DSA
> drivers such as "b53" or "ksz" can be added similarly later. Because
> the different switches supported by mv88e6xxx have slightly different
> register layout, we keep it simple and stupid by providing one dump
> function per switch.
>
> The remaining patches add support for the switch models currently
> supported by the mv88e6xxx driver. Here's an example of dump of the
> 32 registers of a 88E6352 port:
>
> # ethtool -d lan3
> 88E6352 Switch Port Registers
> ------------------------------
> 00: Port Status 0x500f
> Pause Enabled 0
> My Pause 1
> 802.3 PHY Detected 1
> Link Status Down
> Duplex Half
> Speed 10 Mbps
> EEE Enabled 0
> Transmitter Paused 0
> Flow Control 0
> Config Mode 0xf
> 01: Physical Control 0x0003
> RGMII Receive Timing Control Default
> RGMII Transmit Timing Control Default
> 200 BASE Mode 100
> Flow Control's Forced value 0
> Force Flow Control 0
> Link's Forced value Down
> Force Link 0
> Duplex's Forced value Half
> Force Duplex 0
> Force Speed Not forced
> 02: Jamming Control 0x0000
> 03: Switch Identifier 0x3521
> 04: Port Control 0x0433
> Source Address Filtering controls Disabled
> Egress Mode Unmodified
> Ingress & Egress Header Mode 0
> IGMP and MLD Snooping 1
> Frame Mode Normal
> VLAN Tunnel 0
> TagIfBoth 0
> Initial Priority assignment Tag & IP Priority
> Egress Flooding mode No unknown DA
> Port State Forwarding
> 05: Port Control 1 0x0000
> Message Port 0
> Trunk Port 0
> Trunk ID 0
> FID[11:4] 0x000
> 06: Port Base VLAN Map (Header) 0x0060
> FID[3:0] 0x000
> VLANTable 5 6
> 07: Default VLAN ID & Priority 0x0000
> Default Priority 0x0
> Force to use Default VID 0
> Default VLAN Identifier 0
> 08: Port Control 2 0x2080
> Force good FCS in the frame 0
> Jumbo Mode 10240
> 802.1QMode Disabled
> Discard Tagged Frames 0
> Discard Untagged Frames 0
> Map using DA hits 1
> ARP Mirror enable 0
> Egress Monitor Source Port 0
> Ingress Monitor Source Port 0
> Use Default Queue Priority 0
> Default Queue Priority 0x0
> 09: Egress Rate Control 0x0001
> 10: Egress Rate Control 2 0x0000
> 11: Port Association Vector 0x0001
> 12: Port ATU Control 0x0000
> 13: Override 0x0000
> 14: Policy Control 0x0000
> 15: Port Ether Type 0x9100
> 16: InDiscardsLo Frame Counter 0x0000
> 17: InDiscardsHi Frame Counter 0x0000
> 18: InFiltered/TcamCtr Frame Counter 0x0000
> 19: Rx Frame Counter 0x0000
> 20: Reserved 0x0000
> 21: Reserved 0x0000
> 22: LED Control 0x0022
> 23: Reserved 0x0000
> 24: Tag Remap 0-3 0x3210
> 25: Tag Remap 4-7 0x7654
> 26: Reserved 0x0000
> 27: Queue Counters 0x8000
> 28: Reserved 0x0000
> 29: Reserved 0x0000
> 30: Reserved 0x0000
> 31: Reserved 0x0000
>
>
> Changes in v2:
> - read the switch model from regs->version instead of regs[3]
>
>
> Vivien Didelot (7):
> ethtool: dsa: add pretty dump
> ethtool: dsa: mv88e6xxx: add pretty dump
> ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185
> ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161
> ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352
> ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390
> ethtool: dsa: mv88e6xxx: add pretty dump for others
>
> Makefile.am | 2 +-
> dsa.c | 685 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> ethtool.c | 1 +
> internal.h | 3 +
> 4 files changed, 690 insertions(+), 1 deletion(-)
> create mode 100644 dsa.c
Queued for next release.
--
John W. Linville Someday the world will need a hero, and you
linville@tuxdriver.com might be all we have. Be ready.
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-01-18 18:45 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2018-12-18 19:06 [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 1/7] ethtool: dsa: add pretty dump Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 2/7] ethtool: dsa: mv88e6xxx: " Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 3/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185 Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161 Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 5/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352 Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 6/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390 Vivien Didelot
2018-12-18 19:06 ` [PATCH v2 7/7] ethtool: dsa: mv88e6xxx: add pretty dump for others Vivien Didelot
2018-12-19 9:41 ` [PATCH v2 0/7] ethtool: pretty dump mv88e6xxx registers Andrew Lunn
2019-01-18 18:40 ` John W. Linville
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