From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D862CC282C3 for ; Wed, 23 Jan 2019 00:22:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9754521726 for ; Wed, 23 Jan 2019 00:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="yPLnh+a/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726724AbfAWAWp (ORCPT ); Tue, 22 Jan 2019 19:22:45 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:52212 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725985AbfAWAWp (ORCPT ); Tue, 22 Jan 2019 19:22:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=CY0U0UDKVT021gbicYCy+txvHi8NvphLXYmb4m8TNdo=; b=yPLnh+a/wb4oLTUw154g9efws3azvXgozl3hyMo5V4cPOeDgiSZ54X1rstqDSCf9mSO57OuE0DVbQIEPWEE3POYbX6qG+gcrYDpN2a0kIis1lR/3hxM9OtoL17YZ8NDZEdO7jfyNmQBxAvPGTiuxmZtkfW36K0VHg06b3bm0lVY=; Received: from andrew by vps0.lunn.ch with local (Exim 4.84_2) (envelope-from ) id 1gm6JU-0005wU-4b; Wed, 23 Jan 2019 01:22:40 +0100 Date: Wed, 23 Jan 2019 01:22:40 +0100 From: Andrew Lunn To: John David Anglin Cc: Russell King , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org Subject: Re: net: phylink: dsa: mv88e6xxx: flaky link detection on switch ports with internal PHYs Message-ID: <20190123002240.GF3634@lunn.ch> References: <49eec816-9238-c893-0860-602aa8965515@bell.net> <20190122202834.GB12052@lunn.ch> <09fce2e0-9dd2-ea30-7e7d-72f04eede68b@bell.net> <20190122223649.GD3634@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > > It does not need to. There are two options here: > > > > 1) The PHY has no interrupt. phylib will poll the PHY once per second > > for link changes. > > > > 2) The PHY has in interrupt. Link changes will cause the interrupt to > > fire, and the phylib will then read the current state. > > > > For PHYs embedded within a switch driver by mv88e6xxx interrupts > > should always be used. Hi Dave >From my Espressobin cat /proc/interrupts ... 44: 0 0 mv88e6xxx-g1 3 Edge mv88e6xxx-g1-atu-prob 46: 0 0 mv88e6xxx-g1 5 Edge mv88e6xxx-g1-vtu-prob 48: 38 24 mv88e6xxx-g1 7 Edge mv88e6xxx-g2 51: 0 1 mv88e6xxx-g2 1 Edge !soc!internal-regs@d0000000!mdio@32004!switch0@1!mdio:11 52: 0 0 mv88e6xxx-g2 2 Edge !soc!internal-regs@d0000000!mdio@32004!switch0@1!mdio:12 53: 38 23 mv88e6xxx-g2 3 Edge !soc!internal-regs@d0000000!mdio@32004!switch0@1!mdio:13 These are PHY interrupts. > I don't think option 2) is implemented.  Didn't see any irq code in phy.c. You would not. All the interrupt code is in the PHY core and the PHY driver. drivers/net/dsa/mv88e6xxx/phy.c is just a bunch of helpers which allow the mdio bus driver to access phy registers. The PHY driver itself is drivers/net/phy/marvell.c, and the interrupt handling is spread between that and drivers/net/phy/phy.c > If I remember correctly, one needs to use clause 45 accesses to get at > the PHY registers in the 88E6341. Nope. The PHYs are c22 devices. The SERDES are probably C45, but those are not being used here. Andrew