From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 369AFC43381 for ; Fri, 15 Feb 2019 08:34:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DE232190C for ; Fri, 15 Feb 2019 08:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403892AbfBOIeC (ORCPT ); Fri, 15 Feb 2019 03:34:02 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:37839 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730194AbfBOIeB (ORCPT ); Fri, 15 Feb 2019 03:34:01 -0500 Received: from mc-bl-xps13.lan (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) (Authenticated sender: maxime.chevallier@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id E6D3C240009; Fri, 15 Feb 2019 08:33:57 +0000 (UTC) From: Maxime Chevallier To: davem@davemloft.net Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Antoine Tenart , thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com, miquel.raynal@bootlin.com Subject: [PATCH net-next] net: phy: marvell10g: Don't explicitly set Pause and Asym_Pause Date: Fri, 15 Feb 2019 09:33:47 +0100 Message-Id: <20190215083347.5886-1-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The PHY core expects PHY drivers not to set Pause and Asym_Pause bits, unless the driver only wants to specify one of them due to HW limitation. In the case of the Marvell10g driver, we don't need to set them. Signed-off-by: Maxime Chevallier Suggested-by: Andrew Lunn --- drivers/net/phy/marvell10g.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 496805c0ddfe..c04fe5a75129 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -242,9 +242,6 @@ static int mv3310_config_init(struct phy_device *phydev) phydev->interface != PHY_INTERFACE_MODE_10GKR) return -ENODEV; - __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); - __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); - if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); if (val < 0) -- 2.19.2