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[5.150.229.118]) by smtp.gmail.com with ESMTPSA id d9sm3341453lfa.59.2019.02.18.02.28.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 18 Feb 2019 02:28:43 -0800 (PST) Date: Mon, 18 Feb 2019 11:28:41 +0100 From: Niklas Cassel To: Vinod Koul Cc: David S Miller , linux-arm-msm@vger.kernel.org, Bjorn Andersson , netdev@vger.kernel.org, Andrew Lunn , Florian Fainelli , "Nori, Sekhar" , Peter Ujfalusi , Marc Gonzalez Subject: Re: [PATCH v2 2/2] net: phy: at803x: disable delay only for RGMII mode Message-ID: <20190218102841.GB25677@centauri.lan> References: <20190218101853.4290-1-vkoul@kernel.org> <20190218101853.4290-2-vkoul@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190218101853.4290-2-vkoul@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Mon, Feb 18, 2019 at 03:48:53PM +0530, Vinod Koul wrote: > Per "Documentation/devicetree/bindings/net/ethernet.txt" RGMII mode > should not have delay in PHY wheras RGMII_ID and RGMII_RXID/RGMII_TXID > can have delay in phy. > > So disable the delay only for RGMII mode and enable for other modes. > Also treat the default case as disabled delays. > > Fixes: cd28d1d6e52e: ("net: phy: at803x: Disable phy delay for RGMII mode") > Reported-by: Peter Ujfalusi > Signed-off-by: Vinod Koul > --- > drivers/net/phy/at803x.c | 47 ++++++++++++++++++++++++++++++---------- > 1 file changed, 36 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c > index c6e7d800fd7a..dc1b13f7fc12 100644 > --- a/drivers/net/phy/at803x.c > +++ b/drivers/net/phy/at803x.c > @@ -110,6 +110,18 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, > return phy_write(phydev, AT803X_DEBUG_DATA, val); > } > > +static int at803x_enable_rx_delay(struct phy_device *phydev) > +{ > + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, > + AT803X_DEBUG_RX_CLK_DLY_EN); > +} > + > +static int at803x_enable_tx_delay(struct phy_device *phydev) > +{ > + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, > + AT803X_DEBUG_TX_CLK_DLY_EN); > +} > + > static int at803x_disable_rx_delay(struct phy_device *phydev) > { > return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, > @@ -255,23 +267,36 @@ static int at803x_config_init(struct phy_device *phydev) > if (ret < 0) > return ret; > > - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || > - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > - phydev->interface == PHY_INTERFACE_MODE_RGMII) { > - ret = at803x_disable_rx_delay(phydev); > + /* The hardware register default is RX and TX delay enabled, so lets > + * first disable the RX and TX delays in phy and enable them based > + * on the mode selected > + */ > + ret = at803x_disable_rx_delay(phydev); > + if (ret < 0) > + return ret; > + ret = at803x_disable_tx_delay(phydev); > + if (ret < 0) > + return ret; > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { > + /* If RGMII_ID or RGMII_RXID are specified enable RX delay, > + * otherwise keep it disabled > + */ > + ret = at803x_enable_rx_delay(phydev); > if (ret < 0) > return ret; > } > > - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || > - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > - phydev->interface == PHY_INTERFACE_MODE_RGMII) { > - ret = at803x_disable_tx_delay(phydev); > - if (ret < 0) > - return ret; > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { > + /* If RGMII_ID or RGMII_TXID are specified enable TX delay, > + * otherwise keep it disabled > + */ > + ret = at803x_enable_tx_delay(phydev); > } > > - return 0; > + return ret; > } > > static int at803x_ack_interrupt(struct phy_device *phydev) > -- > 2.20.1 > Reviewed-by: Niklas Cassel