From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83626C43381 for ; Mon, 18 Feb 2019 13:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 50E502147A for ; Mon, 18 Feb 2019 13:33:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="TPq7frG/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731071AbfBRNdP (ORCPT ); Mon, 18 Feb 2019 08:33:15 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:56802 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728394AbfBRNdP (ORCPT ); Mon, 18 Feb 2019 08:33:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=eWKu45opC1YoQtShB7Hq2+K3CTJR8sPedMv91eSN+Fc=; b=TPq7frG/JprCDIFMnwbhzUD2dG NQ0443yzQGKjfovDZAG+gOoDq2MA0H121Znv2bEzzozicMy93aElDadpwkkf2E1B8nfiAGoO4OfiJ 0aJj5ra2QXI4HqJwqPcmZLsAl1eYEFAK5AQzvO7cbqHsoRPkrHvHqb71as7g0e8JiaLQ=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1gvj2j-0006Eo-Tf; Mon, 18 Feb 2019 14:33:09 +0100 Date: Mon, 18 Feb 2019 14:33:09 +0100 From: Andrew Lunn To: Vinod Koul Cc: David S Miller , linux-arm-msm@vger.kernel.org, Bjorn Andersson , netdev@vger.kernel.org, Niklas Cassel , Florian Fainelli , Michal =?utf-8?B?Vm9rw6HEjQ==?= Subject: Re: [PATCH] net: dsa: qca8k: Enable delay for RGMII_ID mode Message-ID: <20190218133309.GB14879@lunn.ch> References: <20190218130352.9373-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190218130352.9373-1-vkoul@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Mon, Feb 18, 2019 at 06:33:51PM +0530, Vinod Koul wrote: > RGMII_ID specifies that we should have internal delay, so resurrect the > delay addition routine but under the RGMII_ID mode. > > Fixes: 40269aa9f40a ("net: dsa: qca8k: disable delay for RGMII mode") > Signed-off-by: Vinod Koul > --- > drivers/net/dsa/qca8k.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > index a4b6cda38016..aa1f7f1b20d3 100644 > --- a/drivers/net/dsa/qca8k.c > +++ b/drivers/net/dsa/qca8k.c > @@ -443,6 +443,18 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode) > val = QCA8K_PORT_PAD_RGMII_EN; > qca8k_write(priv, reg, val); > break; > + case PHY_INTERFACE_MODE_RGMII_ID: > + /* RGMII_ID needs internal delay. This is enabled through > + * PORT5_PAD_CTRL for all ports, rather than individual port > + * registers > + */ > + qca8k_write(priv, reg, > + QCA8K_PORT_PAD_RGMII_EN | > + QCA8K_PORT_PAD_RGMII_TX_DELAY(3) | > + QCA8K_PORT_PAD_RGMII_RX_DELAY(3)); > + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, > + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); > + break; Hi Vinod So i'm still confused if this is global, or per-port. The first register written looks to be per-port, although only for ports 0 and 6. The second write seems to be global. Is there a danger that port 0 has PHY_INTERFACE_MODE_RGMII_ID and port 6 has PHY_INTERFACE_MODE_RGMII, and we end up with delays disabled? Maybe we should try to detect this, and return an error? > case PHY_INTERFACE_MODE_SGMII: > qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); > break; I think it would be good to add the other two PHY_INTERFACE_MODE_RGMII modes to the default clause so we get an error reported that they are not implemented. Andrew