From: Andrew Lunn <andrew@lunn.ch>
To: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
netdev@vger.kernel.org,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Mylène Josserand" <mylene.josserand@bootlin.com>
Subject: Re: Handling an Extra Signal at PHY Reset
Date: Tue, 19 Feb 2019 14:36:29 +0100 [thread overview]
Message-ID: <20190219133629.GN14879@lunn.ch> (raw)
In-Reply-To: <e647050a0fbadb8445cf6a7a5a2ccfbfd0865592.camel@bootlin.com>
On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a
> CONFIG pin that must be connected to one of the other pins of the PHY
> to configure the LSB of the PHY address as well as I/O voltages (see
> section 2.18.1 Hardware Configuration of the datasheet). It must be
> connected "soon after reset" for the PHY to be correctly configured.
Hi Paul
I assume there are two PHYs on the MDIO bus, and you need to ensure
they have different addresses? Do we have an Ethernet switch involved
here, or are they two SoC Ethernet networks with one shared MDIO bus?
This seems like an odd design. I've normally seen weak pull up/down
resistors, not a switch, so i'm wondering why it is designed like
this.
Thanks
Andrew
next prev parent reply other threads:[~2019-02-19 13:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-19 9:14 Handling an Extra Signal at PHY Reset Paul Kocialkowski
2019-02-19 9:36 ` Thomas Petazzoni
2019-02-19 12:53 ` Paul Kocialkowski
2019-02-19 13:36 ` Andrew Lunn [this message]
2019-02-19 15:06 ` Paul Kocialkowski
2019-02-19 15:40 ` Andrew Lunn
2019-02-20 8:06 ` Thomas Petazzoni
2019-02-19 16:07 ` Florian Fainelli
2019-02-21 9:05 ` Paul Kocialkowski
2019-02-21 1:49 ` Andrew Lunn
2019-02-21 8:50 ` Paul Kocialkowski
2019-02-21 14:04 ` Andrew Lunn
2019-02-27 8:19 ` Paul Kocialkowski
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