From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83AAFC43381 for ; Wed, 20 Feb 2019 08:06:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5874D21773 for ; Wed, 20 Feb 2019 08:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725865AbfBTIGz (ORCPT ); Wed, 20 Feb 2019 03:06:55 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:35629 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725813AbfBTIGy (ORCPT ); Wed, 20 Feb 2019 03:06:54 -0500 Received: from windsurf (aaubervilliers-681-1-81-190.w90-88.abo.wanadoo.fr [90.88.23.190]) (Authenticated sender: thomas.petazzoni@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 0858224000B; Wed, 20 Feb 2019 08:06:51 +0000 (UTC) Date: Wed, 20 Feb 2019 09:06:51 +0100 From: Thomas Petazzoni To: Andrew Lunn Cc: Paul Kocialkowski , Florian Fainelli , Heiner Kallweit , netdev@vger.kernel.org, =?UTF-8?B?TXlsw6huZQ==?= Josserand Subject: Re: Handling an Extra Signal at PHY Reset Message-ID: <20190220090651.0e00f284@windsurf> In-Reply-To: <20190219133629.GN14879@lunn.ch> References: <20190219133629.GN14879@lunn.ch> Organization: Bootlin X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, 19 Feb 2019 14:36:29 +0100 Andrew Lunn wrote: > This seems like an odd design. I've normally seen weak pull up/down > resistors, not a switch, so i'm wondering why it is designed like > this. The key point here is that this "CONFIG" pin of the PHY is used during reset to configure the PHY, but then once the reset sequence is finished, this pin is used for PTP. From the datasheet, section 2.28.1 "PTP Control": """ To support the PTP Time Stamping function, the device has four pins that are global to the entire PHY: - PTP clock input pin (The CONFIG pin is used for this purpose.) - PTP Event Request input pin (The LED[1] pin is used for this purpose) - PTP Event Request input pin (The LED[1] pin is used for this purpose) - Interrupt Pin (The LED[2] pin is used for this purpose) """ A bit further down in the datasheet: "After configuration is completed and the external clock source is enabled, the CONFIG pin is used as the external 125 Mhz reference clock input" So that's why our design as a switch: it allows the CONFIG pin to be used for configuration during the reset sequence, and then as the pin for the PTP clock input. Does that clarify why the CONFIG pin is not simply connected to some static pull-up/pull-down ? Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com