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received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: gVXS9EkvIfn+871E1dWKoYNEHT5NasPHQ4VO2r0dQ4qUQxnVUNiaEaw5GlLqLk4rXsMzIJ4cT2pqeG04mnJAeI3N6X564R4ECU/xN/JkDkBbBG9UkRY7ZRNSY4H3vejsl0JE8C6vgHFN+18ZGBLXLY4AdNVqIrqAvhxTPW1ijzVE8qnKHn0zdxm8h8g3Cl+cYIIntYalUDPNVmYesxws3deXnszvgD7v6UcrsyeBsYr2P73TtWjm0z5meHqcRw9jrvA3RhBoWfkmGj0nENn9Q6rK3B6a2HDAklPf37k4HeH8sCWgwi6DsyHsmbX6suvPsrZg7Sbd+HblpMt80UBJyooRF1HTLqfF+ERHxAYmZhGKuZnq2PRqFgBBAKbp+fjC4Kq8cUwm5BQveS1BLBUbBq2UvbBkNclu/9VoyP/As3U= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: b545a522-b019-4c72-f278-08d6976a2359 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Feb 2019 19:32:22.3450 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR05MB4871 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Petr Machata The SBMM register configures the shared buffer quota for MC packets according to Switch-Priority. The default configuration depends on the chip type. Therefore keep the table and length in struct mlxsw_sp_sb_vals. Redirect the references from the global definitions to the fields. Signed-off-by: Petr Machata Signed-off-by: Ido Schimmel --- .../mellanox/mlxsw/spectrum_buffers.c | 24 +++++++++++-------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c b/drive= rs/net/ethernet/mellanox/mlxsw/spectrum_buffers.c index 18b182656df2..5194fc8f80cc 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c @@ -37,6 +37,12 @@ struct mlxsw_sp_sb_pm { struct mlxsw_cp_sb_occ occ; }; =20 +struct mlxsw_sp_sb_mm { + u32 min_buff; + u32 max_buff; + u16 pool_index; +}; + struct mlxsw_sp_sb_pool_des { enum mlxsw_reg_sbxx_dir dir; u8 pool; @@ -76,9 +82,11 @@ struct mlxsw_sp_sb_vals { const struct mlxsw_sp_sb_pool_des *pool_dess; const struct mlxsw_sp_sb_pm *pms; const struct mlxsw_sp_sb_pr *prs; + const struct mlxsw_sp_sb_mm *mms; const struct mlxsw_sp_sb_cm *cms_ingress; const struct mlxsw_sp_sb_cm *cms_egress; const struct mlxsw_sp_sb_cm *cms_cpu; + unsigned int mms_count; unsigned int cms_ingress_count; unsigned int cms_egress_count; unsigned int cms_cpu_count; @@ -604,12 +612,6 @@ static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_p= ort *mlxsw_sp_port) return 0; } =20 -struct mlxsw_sp_sb_mm { - u32 min_buff; - u32 max_buff; - u16 pool_index; -}; - #define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool) \ { \ .min_buff =3D _min_buff, \ @@ -635,20 +637,18 @@ static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = =3D { MLXSW_SP_SB_MM(0, 6, 4), }; =20 -#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms) - static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp) { char sbmm_pl[MLXSW_REG_SBMM_LEN]; int i; int err; =20 - for (i =3D 0; i < MLXSW_SP_SB_MMS_LEN; i++) { + for (i =3D 0; i < mlxsw_sp->sb_vals->mms_count; i++) { const struct mlxsw_sp_sb_pool_des *des; const struct mlxsw_sp_sb_mm *mc; u32 min_buff; =20 - mc =3D &mlxsw_sp_sb_mms[i]; + mc =3D &mlxsw_sp->sb_vals->mms[i]; des =3D &mlxsw_sp->sb_vals->pool_dess[mc->pool_index]; /* All pools used by sb_mm's are initialized using dynamic * thresholds, therefore 'max_buff' isn't specified in cells. @@ -684,9 +684,11 @@ const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals =3D { .pool_dess =3D mlxsw_sp_sb_pool_dess, .pms =3D mlxsw_sp_sb_pms, .prs =3D mlxsw_sp_sb_prs, + .mms =3D mlxsw_sp_sb_mms, .cms_ingress =3D mlxsw_sp_sb_cms_ingress, .cms_egress =3D mlxsw_sp_sb_cms_egress, .cms_cpu =3D mlxsw_sp_cpu_port_sb_cms, + .mms_count =3D ARRAY_SIZE(mlxsw_sp_sb_mms), .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_ingress), .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_egress), .cms_cpu_count =3D ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms), @@ -697,9 +699,11 @@ const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals =3D { .pool_dess =3D mlxsw_sp_sb_pool_dess, .pms =3D mlxsw_sp_sb_pms, .prs =3D mlxsw_sp_sb_prs, + .mms =3D mlxsw_sp_sb_mms, .cms_ingress =3D mlxsw_sp_sb_cms_ingress, .cms_egress =3D mlxsw_sp_sb_cms_egress, .cms_cpu =3D mlxsw_sp_cpu_port_sb_cms, + .mms_count =3D ARRAY_SIZE(mlxsw_sp_sb_mms), .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_ingress), .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_egress), .cms_cpu_count =3D ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms), --=20 2.20.1