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received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GQKb7vun9hYT1654EpXCbGdG/pxQk1Nsn+3KoGc2Avj2jORSJ2cAFT0U8Hq+6qGTcB46IrYbmqiOX/Ak7ZAUmwtgHXBKhqzArofTyqsLLm/jIknMGzs6QyvuMxOvpd1Ns5TK4RUUfMEwU5gRYsEXZqr6cGcU8mMuoAVNucnhwTnm2kQiNmGDMaTC4wkXTxaMDOwB6ejwAaBHg/wEPAtfDEZvS4lmYOybihntVeyffYGEo7S1jejuZnfR0hcf1cHQtRdAtLDKlCeEAst5o5F97ongOPZXGMX4i6Y6F/zROeL1o+9/1ytxDF3txUjOmsLEQdIbvxWlsmL/DgTb843m9zy729TOUdeEo+9po879L0xq/JyJuvFvjJHbSSS8+g4o85GJZuPe3UGCMBM/fM5s5PZJkWRGloyzordoG6oWGps= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3082c49b-6755-4db3-da71-08d6976a246f X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Feb 2019 19:32:24.0122 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR05MB4871 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Petr Machata Customize the tables related to shared buffer configuration to match the current recommendation for Spectrum-2 systems. Signed-off-by: Petr Machata Signed-off-by: Ido Schimmel --- .../mellanox/mlxsw/spectrum_buffers.c | 134 ++++++++++++++---- 1 file changed, 106 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c b/drive= rs/net/ethernet/mellanox/mlxsw/spectrum_buffers.c index 5194fc8f80cc..bb327dfe1336 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c @@ -49,7 +49,7 @@ struct mlxsw_sp_sb_pool_des { }; =20 /* Order ingress pools before egress pools. */ -static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] =3D { +static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] =3D { {MLXSW_REG_SBXX_DIR_INGRESS, 0}, {MLXSW_REG_SBXX_DIR_INGRESS, 1}, {MLXSW_REG_SBXX_DIR_INGRESS, 2}, @@ -61,6 +61,17 @@ static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_poo= l_dess[] =3D { {MLXSW_REG_SBXX_DIR_EGRESS, 15}, }; =20 +static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] =3D { + {MLXSW_REG_SBXX_DIR_INGRESS, 0}, + {MLXSW_REG_SBXX_DIR_INGRESS, 1}, + {MLXSW_REG_SBXX_DIR_INGRESS, 2}, + {MLXSW_REG_SBXX_DIR_INGRESS, 3}, + {MLXSW_REG_SBXX_DIR_EGRESS, 0}, + {MLXSW_REG_SBXX_DIR_EGRESS, 1}, + {MLXSW_REG_SBXX_DIR_EGRESS, 2}, + {MLXSW_REG_SBXX_DIR_EGRESS, 3}, +}; + #define MLXSW_SP_SB_ING_TC_COUNT 8 #define MLXSW_SP_SB_EG_TC_COUNT 16 =20 @@ -366,32 +377,53 @@ static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *m= lxsw_sp) kfree(mlxsw_sp->sb->ports); } =20 -#define MLXSW_SP_SB_PR_INGRESS_SIZE 12440000 -#define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000) -#define MLXSW_SP_SB_PR_EGRESS_SIZE 13232000 - #define MLXSW_SP_SB_PR(_mode, _size) \ { \ .mode =3D _mode, \ .size =3D _size, \ } =20 -static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs[] =3D { +#define MLXSW_SP1_SB_PR_INGRESS_SIZE 12440000 +#define MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE (200 * 1000) +#define MLXSW_SP1_SB_PR_EGRESS_SIZE 13232000 + +static const struct mlxsw_sp_sb_pr mlxsw_sp1_sb_prs[] =3D { /* Ingress pools. */ MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, - MLXSW_SP_SB_PR_INGRESS_SIZE), + MLXSW_SP1_SB_PR_INGRESS_SIZE), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, - MLXSW_SP_SB_PR_INGRESS_MNG_SIZE), + MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE), /* Egress pools. */ - MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, MLXSW_SP_SB_PR_EGRESS_SIZE), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, + MLXSW_SP1_SB_PR_EGRESS_SIZE), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI), }; =20 +#define MLXSW_SP2_SB_PR_INGRESS_SIZE 40960000 +#define MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE (200 * 1000) +#define MLXSW_SP2_SB_PR_EGRESS_SIZE 40960000 + +static const struct mlxsw_sp_sb_pr mlxsw_sp2_sb_prs[] =3D { + /* Ingress pools. */ + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, + MLXSW_SP2_SB_PR_INGRESS_SIZE), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, + MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE), + /* Egress pools. */ + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, + MLXSW_SP2_SB_PR_EGRESS_SIZE), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), + MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), +}; + static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp, const struct mlxsw_sp_sb_pr *prs, size_t prs_len) @@ -424,7 +456,7 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_= sp, .pool_index =3D _pool, \ } =20 -static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] =3D { +static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] =3D { MLXSW_SP_SB_CM(10000, 8, 0), MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), @@ -437,7 +469,20 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ing= ress[] =3D { MLXSW_SP_SB_CM(20000, 1, 3), }; =20 -static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] =3D { +static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] =3D { + MLXSW_SP_SB_CM(0, 7, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), + MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */ + MLXSW_SP_SB_CM(20000, 1, 3), +}; + +static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] =3D { MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM(1500, 9, 4), @@ -457,6 +502,26 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egr= ess[] =3D { MLXSW_SP_SB_CM(1, 0xff, 4), }; =20 +static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] =3D { + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(0, 7, 4), + MLXSW_SP_SB_CM(1, 0xff, 4), +}; + #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4) =20 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] =3D { @@ -575,7 +640,7 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_s= p *mlxsw_sp) .max_buff =3D _max_buff, \ } =20 -static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] =3D { +static const struct mlxsw_sp_sb_pm mlxsw_sp1_sb_pms[] =3D { /* Ingress pools. */ MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX), MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), @@ -589,6 +654,19 @@ static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = =3D { MLXSW_SP_SB_PM(10000, 90000), }; =20 +static const struct mlxsw_sp_sb_pm mlxsw_sp2_sb_pms[] =3D { + /* Ingress pools. */ + MLXSW_SP_SB_PM(0, 7), + MLXSW_SP_SB_PM(0, 0), + MLXSW_SP_SB_PM(0, 0), + MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX), + /* Egress pools. */ + MLXSW_SP_SB_PM(0, 7), + MLXSW_SP_SB_PM(0, 0), + MLXSW_SP_SB_PM(0, 0), + MLXSW_SP_SB_PM(0, 0), +}; + static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port) { struct mlxsw_sp *mlxsw_sp =3D mlxsw_sp_port->mlxsw_sp; @@ -680,32 +758,32 @@ static void mlxsw_sp_pool_count(struct mlxsw_sp *mlxs= w_sp, } =20 const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals =3D { - .pool_count =3D ARRAY_SIZE(mlxsw_sp_sb_pool_dess), - .pool_dess =3D mlxsw_sp_sb_pool_dess, - .pms =3D mlxsw_sp_sb_pms, - .prs =3D mlxsw_sp_sb_prs, + .pool_count =3D ARRAY_SIZE(mlxsw_sp1_sb_pool_dess), + .pool_dess =3D mlxsw_sp1_sb_pool_dess, + .pms =3D mlxsw_sp1_sb_pms, + .prs =3D mlxsw_sp1_sb_prs, .mms =3D mlxsw_sp_sb_mms, - .cms_ingress =3D mlxsw_sp_sb_cms_ingress, - .cms_egress =3D mlxsw_sp_sb_cms_egress, + .cms_ingress =3D mlxsw_sp1_sb_cms_ingress, + .cms_egress =3D mlxsw_sp1_sb_cms_egress, .cms_cpu =3D mlxsw_sp_cpu_port_sb_cms, .mms_count =3D ARRAY_SIZE(mlxsw_sp_sb_mms), - .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_ingress), - .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_egress), + .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp1_sb_cms_ingress), + .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp1_sb_cms_egress), .cms_cpu_count =3D ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms), }; =20 const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals =3D { - .pool_count =3D ARRAY_SIZE(mlxsw_sp_sb_pool_dess), - .pool_dess =3D mlxsw_sp_sb_pool_dess, - .pms =3D mlxsw_sp_sb_pms, - .prs =3D mlxsw_sp_sb_prs, + .pool_count =3D ARRAY_SIZE(mlxsw_sp2_sb_pool_dess), + .pool_dess =3D mlxsw_sp2_sb_pool_dess, + .pms =3D mlxsw_sp2_sb_pms, + .prs =3D mlxsw_sp2_sb_prs, .mms =3D mlxsw_sp_sb_mms, - .cms_ingress =3D mlxsw_sp_sb_cms_ingress, - .cms_egress =3D mlxsw_sp_sb_cms_egress, + .cms_ingress =3D mlxsw_sp2_sb_cms_ingress, + .cms_egress =3D mlxsw_sp2_sb_cms_egress, .cms_cpu =3D mlxsw_sp_cpu_port_sb_cms, .mms_count =3D ARRAY_SIZE(mlxsw_sp_sb_mms), - .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_ingress), - .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp_sb_cms_egress), + .cms_ingress_count =3D ARRAY_SIZE(mlxsw_sp2_sb_cms_ingress), + .cms_egress_count =3D ARRAY_SIZE(mlxsw_sp2_sb_cms_egress), .cms_cpu_count =3D ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms), }; =20 --=20 2.20.1