From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C95FDC43381 for ; Sun, 24 Feb 2019 17:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BCA820661 for ; Sun, 24 Feb 2019 17:28:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="SVGCm5hB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728176AbfBXR2w (ORCPT ); Sun, 24 Feb 2019 12:28:52 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:36903 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726206AbfBXR2w (ORCPT ); Sun, 24 Feb 2019 12:28:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=taoci0h3riMApfxRBR2mLYyEo9cCd47aQ/ZiIiDe8rs=; b=SVGCm5hBiS2oBJ+M9sB4ylNjlY cNXP6iqwbTPXLJ5ipiI0JGemrAjKV/6HRHktCzaDfptLsH6a6prsvSbv5w2utGtmz9vaI22fMjQru 8HpRARpYgJ/6EZc2NjFVq7LEW2+fzP1v+fO6GuV0zkIQrJHRGaQmXBsTeBCgrTveYgT8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1gxxa5-0004Z1-0S; Sun, 24 Feb 2019 18:28:49 +0100 Date: Sun, 24 Feb 2019 18:28:48 +0100 From: Andrew Lunn To: Russell King - ARM Linux admin Cc: Heiner Kallweit , Florian Fainelli , "netdev@vger.kernel.org" Subject: Re: No traffic with Marvell switch and latest linux-next Message-ID: <20190224172848.GI26626@lunn.ch> References: <291e7622-4402-e58f-503c-ffc7c6b2f055@gmail.com> <20190217165730.GF5968@lunn.ch> <20190217171027.GH5968@lunn.ch> <33f9ef8d-df62-e154-f880-f886abf54e0a@gmail.com> <20190218182136.GE14879@lunn.ch> <188fcef7-81fe-cffc-af71-1f37725b8611@gmail.com> <20190223234235.GA26626@lunn.ch> <20190224153125.f2n3xfjyjswd7ioa@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190224153125.f2n3xfjyjswd7ioa@shell.armlinux.org.uk> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sun, Feb 24, 2019 at 03:31:26PM +0000, Russell King - ARM Linux admin wrote: > On Sun, Feb 24, 2019 at 12:42:35AM +0100, Andrew Lunn wrote: > > Looking forward, at some point we are going to have to make fixed-link > > support higher speeds. That probably means we need a swphy-c45 which > > emulates the standard registers for 2.5G, 5G and 10G. At that point > > genphy will not work... > > Do we _need_ to emulate Clause 45 PHYs? Hi Russell One use case would be a mv88e6390X port 9 or 10 connected to a SoC which can only do 2.5G. We have defined that DSA drivers should configure CPU and DSA ports to their maximum speed. So if port 9 or 10 is used, it should be configured to 10G. We then need some way to reconfigure the MAC to a slower speed. We need to do this with ZII boards. We do this with: port@0 { reg = <0>; label = "cpu"; ethernet = <&fec1>; fixed-link { speed = <100>; full-duplex; }; }; The FEC can only do 100Mbs, but the switch defaults to 1G. So the fixed link it used to tell the switch MAC to use 100/Full. In the example of the 6390X, we would want to set the link speed to 2500, which we cannot do at the moment. Either we need fixed-link to support higher speeds, or we need a different mechanism. We also have a similar issue on the SoC side. The FEC has no PHY connected to it. It needs to be told what speed to do: &fec1 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; status = "okay"; fixed-link { speed = <100>; full-duplex; }; In the case of a SoC with an interface which can do 2.5G, you need to tell it to do 2.5G. Ideally we want a mechanism that allows a MAC to 'see' a PHY operating at 2.5G using the standard phylib/phylink API. In the past this has been achieved with an emulated PHY. But so long as the phydev/phylink structure has the correct values, it does not matter how they get those values. Andrew