From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AAA1C43381 for ; Mon, 25 Feb 2019 18:43:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1942620C01 for ; Mon, 25 Feb 2019 18:43:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729001AbfBYSnh (ORCPT ); Mon, 25 Feb 2019 13:43:37 -0500 Received: from mga02.intel.com ([134.134.136.20]:17912 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728920AbfBYSnP (ORCPT ); Mon, 25 Feb 2019 13:43:15 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2019 10:43:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,412,1544515200"; d="scan'208";a="137088381" Received: from jtkirshe-desk1.jf.intel.com ([134.134.177.96]) by orsmga002.jf.intel.com with ESMTP; 25 Feb 2019 10:43:12 -0800 From: Jeff Kirsher To: davem@davemloft.net Cc: Brett Creeley , netdev@vger.kernel.org, nhorman@redhat.com, sassmann@redhat.com, Anirudh Venkataramanan , Andrew Bowers , Jeff Kirsher Subject: [net-next 07/16] ice: fix issue where host reboots on unload when iommu=on Date: Mon, 25 Feb 2019 10:42:57 -0800 Message-Id: <20190225184306.13505-8-jeffrey.t.kirsher@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190225184306.13505-1-jeffrey.t.kirsher@intel.com> References: <20190225184306.13505-1-jeffrey.t.kirsher@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Brett Creeley Currently if the kernel has the intel_iommu=on parameter set, on some platforms removing the driver causes a system reboot. In initialization we associate the control queue interrupts with the pf->hw_oicr_idx and enable the interrupts by setting the CAUSE_ENA bit. The problem comes on teardown because we are not clearing the CAUSE_ENA bit for the control queues, but the vector at pf->hw_oicr_idx (miscellaneous interrupt vector) gets disabled. Fix this by clearing the CAUSE_ENA bit in the appropriate control queue registers on when freeing the miscellaneous interrupt vector. Also, move the call to ice_free_irq_msix_misc() to after ice_deinit_sw() in ice_remove() because ice_deinit_sw() makes an AQ call, but ice_free_irq_msix_misc() disables the miscellaneous vector and it's associated interrupts. Also, create two small helper functions to enable and disable the control queue interrupts respectively. Signed-off-by: Brett Creeley Signed-off-by: Anirudh Venkataramanan Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher --- drivers/net/ethernet/intel/ice/ice_main.c | 71 +++++++++++++++++------ 1 file changed, 54 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index aff348e42562..fb04a5ebdc0b 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -1355,15 +1355,40 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data) return ret; } +/** + * ice_dis_ctrlq_interrupts - disable control queue interrupts + * @hw: pointer to HW structure + */ +static void ice_dis_ctrlq_interrupts(struct ice_hw *hw) +{ + /* disable Admin queue Interrupt causes */ + wr32(hw, PFINT_FW_CTL, + rd32(hw, PFINT_FW_CTL) & ~PFINT_FW_CTL_CAUSE_ENA_M); + + /* disable Mailbox queue Interrupt causes */ + wr32(hw, PFINT_MBX_CTL, + rd32(hw, PFINT_MBX_CTL) & ~PFINT_MBX_CTL_CAUSE_ENA_M); + + /* disable Control queue Interrupt causes */ + wr32(hw, PFINT_OICR_CTL, + rd32(hw, PFINT_OICR_CTL) & ~PFINT_OICR_CTL_CAUSE_ENA_M); + + ice_flush(hw); +} + /** * ice_free_irq_msix_misc - Unroll misc vector setup * @pf: board private structure */ static void ice_free_irq_msix_misc(struct ice_pf *pf) { + struct ice_hw *hw = &pf->hw; + + ice_dis_ctrlq_interrupts(hw); + /* disable OICR interrupt */ - wr32(&pf->hw, PFINT_OICR_ENA, 0); - ice_flush(&pf->hw); + wr32(hw, PFINT_OICR_ENA, 0); + ice_flush(hw); if (test_bit(ICE_FLAG_MSIX_ENA, pf->flags) && pf->msix_entries) { synchronize_irq(pf->msix_entries[pf->sw_oicr_idx].vector); @@ -1377,6 +1402,32 @@ static void ice_free_irq_msix_misc(struct ice_pf *pf) ice_free_res(pf->hw_irq_tracker, pf->hw_oicr_idx, ICE_RES_MISC_VEC_ID); } +/** + * ice_ena_ctrlq_interrupts - enable control queue interrupts + * @hw: pointer to HW structure + * @v_idx: HW vector index to associate the control queue interrupts with + */ +static void ice_ena_ctrlq_interrupts(struct ice_hw *hw, u16 v_idx) +{ + u32 val; + + val = ((v_idx & PFINT_OICR_CTL_MSIX_INDX_M) | + PFINT_OICR_CTL_CAUSE_ENA_M); + wr32(hw, PFINT_OICR_CTL, val); + + /* enable Admin queue Interrupt causes */ + val = ((v_idx & PFINT_FW_CTL_MSIX_INDX_M) | + PFINT_FW_CTL_CAUSE_ENA_M); + wr32(hw, PFINT_FW_CTL, val); + + /* enable Mailbox queue Interrupt causes */ + val = ((v_idx & PFINT_MBX_CTL_MSIX_INDX_M) | + PFINT_MBX_CTL_CAUSE_ENA_M); + wr32(hw, PFINT_MBX_CTL, val); + + ice_flush(hw); +} + /** * ice_req_irq_msix_misc - Setup the misc vector to handle non queue events * @pf: board private structure @@ -1389,7 +1440,6 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf) { struct ice_hw *hw = &pf->hw; int oicr_idx, err = 0; - u32 val; if (!pf->int_name[0]) snprintf(pf->int_name, sizeof(pf->int_name) - 1, "%s-%s:misc", @@ -1438,20 +1488,7 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf) skip_req_irq: ice_ena_misc_vector(pf); - val = ((pf->hw_oicr_idx & PFINT_OICR_CTL_MSIX_INDX_M) | - PFINT_OICR_CTL_CAUSE_ENA_M); - wr32(hw, PFINT_OICR_CTL, val); - - /* This enables Admin queue Interrupt causes */ - val = ((pf->hw_oicr_idx & PFINT_FW_CTL_MSIX_INDX_M) | - PFINT_FW_CTL_CAUSE_ENA_M); - wr32(hw, PFINT_FW_CTL, val); - - /* This enables Mailbox queue Interrupt causes */ - val = ((pf->hw_oicr_idx & PFINT_MBX_CTL_MSIX_INDX_M) | - PFINT_MBX_CTL_CAUSE_ENA_M); - wr32(hw, PFINT_MBX_CTL, val); - + ice_ena_ctrlq_interrupts(hw, pf->hw_oicr_idx); wr32(hw, GLINT_ITR(ICE_RX_ITR, pf->hw_oicr_idx), ITR_REG_ALIGN(ICE_ITR_8K) >> ICE_ITR_GRAN_S); -- 2.20.1