* [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support
@ 2019-04-13 16:51 Heiner Kallweit
2019-04-13 16:52 ` [PATCH net-next 1/2] net: phy: shrink PHY settings array Heiner Kallweit
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Heiner Kallweit @ 2019-04-13 16:51 UTC (permalink / raw)
To: Andrew Lunn, Florian Fainelli, David Miller,
netdev@vger.kernel.org
The definition of array settings[] is quite lengthy meanwhile. Add a
macro to shrink the definition.
When doing this I saw that the new 200Gbps modes aren't supported
in phylib yet. So add this. I think we need to document somewhere
which places in phylib need to be touched if a new speed / mode is
added.
Heiner Kallweit (2):
net: phy: shrink PHY settings array
net: phy: add 200Gbps support to phylib
drivers/net/phy/phy-core.c | 255 ++++++++-----------------------------
1 file changed, 53 insertions(+), 202 deletions(-)
--
2.21.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH net-next 1/2] net: phy: shrink PHY settings array 2019-04-13 16:51 [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Heiner Kallweit @ 2019-04-13 16:52 ` Heiner Kallweit 2019-04-13 17:14 ` Andrew Lunn 2019-04-13 16:53 ` [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib Heiner Kallweit ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: Heiner Kallweit @ 2019-04-13 16:52 UTC (permalink / raw) To: Andrew Lunn, Florian Fainelli, David Miller, netdev@vger.kernel.org The definition of array settings[] is quite lengthy meanwhile. Add a macro to shrink the definition. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> --- drivers/net/phy/phy-core.c | 247 +++++++------------------------------ 1 file changed, 45 insertions(+), 202 deletions(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 5016cd5fd..7bfcfb0fd 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -58,222 +58,65 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str); /* A mapping of all SUPPORTED settings to speed/duplex. This table * must be grouped by speed and sorted in descending match priority * - iow, descending speed. */ + +#define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \ + .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} + static const struct phy_setting settings[] = { /* 100G */ - { - .speed = SPEED_100000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, - }, - { - .speed = SPEED_100000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, - }, - { - .speed = SPEED_100000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, - }, - { - .speed = SPEED_100000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, - }, + PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), + PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), + PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), + PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), /* 56G */ - { - .speed = SPEED_56000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, - }, - { - .speed = SPEED_56000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, - }, - { - .speed = SPEED_56000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, - }, - { - .speed = SPEED_56000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, - }, + PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), + PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), + PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), + PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), /* 50G */ - { - .speed = SPEED_50000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, - }, - { - .speed = SPEED_50000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, - }, - { - .speed = SPEED_50000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, - }, + PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), + PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), + PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), /* 40G */ - { - .speed = SPEED_40000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, - }, - { - .speed = SPEED_40000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, - }, - { - .speed = SPEED_40000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, - }, - { - .speed = SPEED_40000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, - }, + PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), + PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), + PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), + PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), /* 25G */ - { - .speed = SPEED_25000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, - }, - { - .speed = SPEED_25000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, - }, - { - .speed = SPEED_25000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, - }, - + PHY_SETTING( 25000, FULL, 25000baseCR_Full ), + PHY_SETTING( 25000, FULL, 25000baseKR_Full ), + PHY_SETTING( 25000, FULL, 25000baseSR_Full ), /* 20G */ - { - .speed = SPEED_20000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, - }, - { - .speed = SPEED_20000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT, - }, + PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), + PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), /* 10G */ - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseER_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, - }, - { - .speed = SPEED_10000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - }, + PHY_SETTING( 10000, FULL, 10000baseCR_Full ), + PHY_SETTING( 10000, FULL, 10000baseER_Full ), + PHY_SETTING( 10000, FULL, 10000baseKR_Full ), + PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), + PHY_SETTING( 10000, FULL, 10000baseLR_Full ), + PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), + PHY_SETTING( 10000, FULL, 10000baseR_FEC ), + PHY_SETTING( 10000, FULL, 10000baseSR_Full ), + PHY_SETTING( 10000, FULL, 10000baseT_Full ), /* 5G */ - { - .speed = SPEED_5000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - }, - + PHY_SETTING( 5000, FULL, 5000baseT_Full ), /* 2.5G */ - { - .speed = SPEED_2500, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - }, - { - .speed = SPEED_2500, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT, - }, + PHY_SETTING( 2500, FULL, 2500baseT_Full ), + PHY_SETTING( 2500, FULL, 2500baseX_Full ), /* 1G */ - { - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, - }, - { - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - }, - { - .speed = SPEED_1000, - .duplex = DUPLEX_HALF, - .bit = ETHTOOL_LINK_MODE_1000baseT_Half_BIT, - }, - { - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, - }, + PHY_SETTING( 1000, FULL, 1000baseKX_Full ), + PHY_SETTING( 1000, FULL, 1000baseT_Full ), + PHY_SETTING( 1000, HALF, 1000baseT_Half ), + PHY_SETTING( 1000, FULL, 1000baseX_Full ), /* 100M */ - { - .speed = SPEED_100, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_100baseT_Full_BIT, - }, - { - .speed = SPEED_100, - .duplex = DUPLEX_HALF, - .bit = ETHTOOL_LINK_MODE_100baseT_Half_BIT, - }, + PHY_SETTING( 100, FULL, 100baseT_Full ), + PHY_SETTING( 100, HALF, 100baseT_Half ), /* 10M */ - { - .speed = SPEED_10, - .duplex = DUPLEX_FULL, - .bit = ETHTOOL_LINK_MODE_10baseT_Full_BIT, - }, - { - .speed = SPEED_10, - .duplex = DUPLEX_HALF, - .bit = ETHTOOL_LINK_MODE_10baseT_Half_BIT, - }, + PHY_SETTING( 10, FULL, 10baseT_Full ), + PHY_SETTING( 10, HALF, 10baseT_Half ), }; +#undef PHY_SETTING /** * phy_lookup_setting - lookup a PHY setting -- 2.21.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 1/2] net: phy: shrink PHY settings array 2019-04-13 16:52 ` [PATCH net-next 1/2] net: phy: shrink PHY settings array Heiner Kallweit @ 2019-04-13 17:14 ` Andrew Lunn 2019-04-13 17:28 ` Heiner Kallweit 0 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2019-04-13 17:14 UTC (permalink / raw) To: Heiner Kallweit; +Cc: Florian Fainelli, David Miller, netdev@vger.kernel.org > + PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), > + PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), > + PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), > + PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), > + PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), > + PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), > + PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), > + PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), > + PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), > + PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), > + PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), > + PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), > + PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), > + PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), > + PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), > + PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), > + PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), > + PHY_SETTING( 10000, FULL, 10000baseCR_Full ), > + PHY_SETTING( 10000, FULL, 10000baseER_Full ), > + PHY_SETTING( 10000, FULL, 10000baseKR_Full ), > + PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), > + PHY_SETTING( 10000, FULL, 10000baseLR_Full ), > + PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), > + PHY_SETTING( 10000, FULL, 10000baseR_FEC ), > + PHY_SETTING( 10000, FULL, 10000baseSR_Full ), > + PHY_SETTING( 10000, FULL, 10000baseT_Full ), > + PHY_SETTING( 2500, FULL, 2500baseT_Full ), > + PHY_SETTING( 2500, FULL, 2500baseX_Full ), > + PHY_SETTING( 1000, FULL, 1000baseKX_Full ), > + PHY_SETTING( 1000, FULL, 1000baseT_Full ), > + PHY_SETTING( 1000, HALF, 1000baseT_Half ), > + PHY_SETTING( 1000, FULL, 1000baseX_Full ), > + PHY_SETTING( 100, FULL, 100baseT_Full ), > + PHY_SETTING( 100, HALF, 100baseT_Half ), > + PHY_SETTING( 10, FULL, 10baseT_Full ), > + PHY_SETTING( 10, HALF, 10baseT_Half ), I like the spaces here for the speed. I know i've missed counted the number of 0 and put entries in the wrong place. Maybe 2500base* and later could be indented by one more space, so that 'base' is always in the same column? Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 1/2] net: phy: shrink PHY settings array 2019-04-13 17:14 ` Andrew Lunn @ 2019-04-13 17:28 ` Heiner Kallweit 0 siblings, 0 replies; 10+ messages in thread From: Heiner Kallweit @ 2019-04-13 17:28 UTC (permalink / raw) To: Andrew Lunn; +Cc: Florian Fainelli, David Miller, netdev@vger.kernel.org On 13.04.2019 19:14, Andrew Lunn wrote: >> + PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), >> + PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), >> + PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), >> + PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), >> + PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), >> + PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), >> + PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), >> + PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), >> + PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), >> + PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), >> + PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), >> + PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), >> + PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), >> + PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), >> + PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), >> + PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), >> + PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseCR_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseER_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseKR_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseLR_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseR_FEC ), >> + PHY_SETTING( 10000, FULL, 10000baseSR_Full ), >> + PHY_SETTING( 10000, FULL, 10000baseT_Full ), >> + PHY_SETTING( 2500, FULL, 2500baseT_Full ), >> + PHY_SETTING( 2500, FULL, 2500baseX_Full ), >> + PHY_SETTING( 1000, FULL, 1000baseKX_Full ), >> + PHY_SETTING( 1000, FULL, 1000baseT_Full ), >> + PHY_SETTING( 1000, HALF, 1000baseT_Half ), >> + PHY_SETTING( 1000, FULL, 1000baseX_Full ), >> + PHY_SETTING( 100, FULL, 100baseT_Full ), >> + PHY_SETTING( 100, HALF, 100baseT_Half ), >> + PHY_SETTING( 10, FULL, 10baseT_Full ), >> + PHY_SETTING( 10, HALF, 10baseT_Half ), > > I like the spaces here for the speed. I know i've missed counted the > number of 0 and put entries in the wrong place. Maybe 2500base* and > later could be indented by one more space, so that 'base' is always in > the same column? > Indeed, one space is missing for the modes <= 2500. > Andrew > Heiner ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib 2019-04-13 16:51 [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Heiner Kallweit 2019-04-13 16:52 ` [PATCH net-next 1/2] net: phy: shrink PHY settings array Heiner Kallweit @ 2019-04-13 16:53 ` Heiner Kallweit 2019-04-13 17:14 ` Andrew Lunn 2019-04-13 17:07 ` [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Andrew Lunn 2019-04-14 20:29 ` David Miller 3 siblings, 1 reply; 10+ messages in thread From: Heiner Kallweit @ 2019-04-13 16:53 UTC (permalink / raw) To: Andrew Lunn, Florian Fainelli, David Miller, netdev@vger.kernel.org Recently 200Gbps modes have been added to ethtool.h, but the related extension to phylib hasn't been done yet. So add support for these modes. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> --- drivers/net/phy/phy-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 7bfcfb0fd..4af19ceae 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -35,6 +35,8 @@ const char *phy_speed_to_str(int speed) return "56Gbps"; case SPEED_100000: return "100Gbps"; + case SPEED_200000: + return "200Gbps"; case SPEED_UNKNOWN: return "Unknown"; default: @@ -63,6 +65,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str); .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} static const struct phy_setting settings[] = { + /* 200G */ + PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), + PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), + PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ), + PHY_SETTING( 200000, FULL, 200000baseDR4_Full ), + PHY_SETTING( 200000, FULL, 200000baseSR4_Full ), /* 100G */ PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), -- 2.21.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib 2019-04-13 16:53 ` [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib Heiner Kallweit @ 2019-04-13 17:14 ` Andrew Lunn 0 siblings, 0 replies; 10+ messages in thread From: Andrew Lunn @ 2019-04-13 17:14 UTC (permalink / raw) To: Heiner Kallweit; +Cc: Florian Fainelli, David Miller, netdev@vger.kernel.org On Sat, Apr 13, 2019 at 06:53:30PM +0200, Heiner Kallweit wrote: > Recently 200Gbps modes have been added to ethtool.h, but the related > extension to phylib hasn't been done yet. So add support for these > modes. > > Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support 2019-04-13 16:51 [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Heiner Kallweit 2019-04-13 16:52 ` [PATCH net-next 1/2] net: phy: shrink PHY settings array Heiner Kallweit 2019-04-13 16:53 ` [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib Heiner Kallweit @ 2019-04-13 17:07 ` Andrew Lunn 2019-04-13 17:26 ` Heiner Kallweit 2019-04-14 20:29 ` David Miller 3 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2019-04-13 17:07 UTC (permalink / raw) To: Heiner Kallweit; +Cc: Florian Fainelli, David Miller, netdev@vger.kernel.org On Sat, Apr 13, 2019 at 06:51:16PM +0200, Heiner Kallweit wrote: > The definition of array settings[] is quite lengthy meanwhile. Add a > macro to shrink the definition. > > When doing this I saw that the new 200Gbps modes aren't supported > in phylib yet. So add this. I think we need to document somewhere > which places in phylib need to be touched if a new speed / mode is > added. Yes, maybe something like BUILD_BUG_ON(__ETHTOOL_LINK_MODE_MASK_NBITS != 67); in drivers/net/phy/phy-core.c with a comment explaining what should be done? Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support 2019-04-13 17:07 ` [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Andrew Lunn @ 2019-04-13 17:26 ` Heiner Kallweit 0 siblings, 0 replies; 10+ messages in thread From: Heiner Kallweit @ 2019-04-13 17:26 UTC (permalink / raw) To: Andrew Lunn; +Cc: Florian Fainelli, David Miller, netdev@vger.kernel.org On 13.04.2019 19:07, Andrew Lunn wrote: > On Sat, Apr 13, 2019 at 06:51:16PM +0200, Heiner Kallweit wrote: >> The definition of array settings[] is quite lengthy meanwhile. Add a >> macro to shrink the definition. >> >> When doing this I saw that the new 200Gbps modes aren't supported >> in phylib yet. So add this. I think we need to document somewhere >> which places in phylib need to be touched if a new speed / mode is >> added. > > Yes, maybe something like > > BUILD_BUG_ON(__ETHTOOL_LINK_MODE_MASK_NBITS != 67); > > in drivers/net/phy/phy-core.c with a comment explaining what should be > done? > Yes, this sounds reasonable. We could use BUILD_BUG_ON_MSG to print this comment. > Andrew > Heiner ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support 2019-04-13 16:51 [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Heiner Kallweit ` (2 preceding siblings ...) 2019-04-13 17:07 ` [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Andrew Lunn @ 2019-04-14 20:29 ` David Miller 2019-04-14 20:30 ` Heiner Kallweit 3 siblings, 1 reply; 10+ messages in thread From: David Miller @ 2019-04-14 20:29 UTC (permalink / raw) To: hkallweit1; +Cc: andrew, f.fainelli, netdev From: Heiner Kallweit <hkallweit1@gmail.com> Date: Sat, 13 Apr 2019 18:51:16 +0200 > The definition of array settings[] is quite lengthy meanwhile. Add a > macro to shrink the definition. > > When doing this I saw that the new 200Gbps modes aren't supported > in phylib yet. So add this. I think we need to document somewhere > which places in phylib need to be touched if a new speed / mode is > added. I assume this will be respun with some slight formatting changes to patch #1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support 2019-04-14 20:29 ` David Miller @ 2019-04-14 20:30 ` Heiner Kallweit 0 siblings, 0 replies; 10+ messages in thread From: Heiner Kallweit @ 2019-04-14 20:30 UTC (permalink / raw) To: David Miller; +Cc: andrew, f.fainelli, netdev On 14.04.2019 22:29, David Miller wrote: > From: Heiner Kallweit <hkallweit1@gmail.com> > Date: Sat, 13 Apr 2019 18:51:16 +0200 > >> The definition of array settings[] is quite lengthy meanwhile. Add a >> macro to shrink the definition. >> >> When doing this I saw that the new 200Gbps modes aren't supported >> in phylib yet. So add this. I think we need to document somewhere >> which places in phylib need to be touched if a new speed / mode is >> added. > > I assume this will be respun with some slight formatting changes to > patch #1 > Right. A v2 series with three patches was submitted already. ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-04-14 20:31 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-04-13 16:51 [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Heiner Kallweit 2019-04-13 16:52 ` [PATCH net-next 1/2] net: phy: shrink PHY settings array Heiner Kallweit 2019-04-13 17:14 ` Andrew Lunn 2019-04-13 17:28 ` Heiner Kallweit 2019-04-13 16:53 ` [PATCH net-next 2/2] net: phy: add 200Gbps support to phylib Heiner Kallweit 2019-04-13 17:14 ` Andrew Lunn 2019-04-13 17:07 ` [PATCH net-next 0/2] net: phy: shrink PHY settings array and add 200Gbps support Andrew Lunn 2019-04-13 17:26 ` Heiner Kallweit 2019-04-14 20:29 ` David Miller 2019-04-14 20:30 ` Heiner Kallweit
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