From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BDFFC43219 for ; Sat, 27 Apr 2019 15:36:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 19C5B206C1 for ; Sat, 27 Apr 2019 15:36:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="KnqW2PP/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726688AbfD0PgB (ORCPT ); Sat, 27 Apr 2019 11:36:01 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:46597 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725942AbfD0PgA (ORCPT ); Sat, 27 Apr 2019 11:36:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=V45wpnfLeQOSYBX0MOGnG8rMOzfUKNaMEi9DPEGLJQo=; b=KnqW2PP/6azPkPb++4yC6VAk4q 4zg1m8J+Sj1SabVwhyOqIB7lnaUzVRswP3yL0/FOZTQKJxLLBEeDCW3eCoI21LacDJxjFLcxSi08Q ui3hN4rzSTt5BXH7pMTOzO4UHSRffFNU+ofHQxfY2YPkZQJSLoiI/U/ibJe5kgW8pwIY=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1hKPMq-0002GR-Be; Sat, 27 Apr 2019 17:35:56 +0200 Date: Sat, 27 Apr 2019 17:35:56 +0200 From: Andrew Lunn To: Igor Russkikh Cc: "David S . Miller" , "netdev@vger.kernel.org" , Nikita Danilov , Dmitry Bogdanov Subject: Re: [PATCH v3 net-next 14/15] net: aquantia: fixups on 64bit dma counters Message-ID: <20190427153556.GK14432@lunn.ch> References: <20190426213639.GS4041@lunn.ch> <14845b14-a05e-9c1c-b43b-7b9b70729808@aquantia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <14845b14-a05e-9c1c-b43b-7b9b70729808@aquantia.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sat, Apr 27, 2019 at 06:28:12AM +0000, Igor Russkikh wrote: > > > On 27.04.2019 0:36, Andrew Lunn wrote: > >> + self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self) + > >> + ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); > > > > Don't you need to do something to avoid issue with overflow from lsw > > into msw? I've often seen code get the msw, the lsw and then the msm > > again. If the two msw reads are different, it repeats it all again. > > Hardware latches msw when host reads lsw register. So thats safe. > > However looking into spec it says to always read lsw first. > The syntax above does not guarantee that in general. > I'll change that with something like > > dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self); > dma_pkt_rc |= ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); Hi Igor I think i would probably have a hw_atl_stats_rx_dma_good_pkt_counter() which returns a u64. Under that, have a aq_hw_read_reg64() which does things in the correct ordering, and a comment about reading the lsw latches the msw. Andrew