From: Andrew Lunn <andrew@lunn.ch>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>,
netdev@vger.kernel.org, davem@davemloft.net,
joabreu@synopsys.com, Wei Liang Lim <wei.liang.lim@intel.com>
Subject: Re: [PATCH net-next] net: stmmac: socfpga: add RMII phy mode
Date: Wed, 15 May 2019 18:30:41 +0200 [thread overview]
Message-ID: <20190515163041.GB24455@lunn.ch> (raw)
In-Reply-To: <cbe79f88-2f4c-a5bc-7dcd-e1dac253a787@gmail.com>
On Wed, May 15, 2019 at 09:18:15AM -0700, Florian Fainelli wrote:
> On 5/15/19 8:24 AM, Andrew Lunn wrote:
> >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> >> @@ -251,6 +251,9 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
> >> case PHY_INTERFACE_MODE_SGMII:
> >> val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
> >> break;
> >> + case PHY_INTERFACE_MODE_RMII:
> >> + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
> >> + break;
> >
> > What about PHY_INTERFACE_MODE_RMII_ID, PHY_INTERFACE_MODE_RMII_RXID,
> > PHY_INTERFACE_MODE_RMII_TXID?
>
> RMII is reduced MII not Reduced Gigabit MII (RGMII), which still
> operates at MII speed, therefore no concept of internal deal for RX/TX
> data lines, the change looks fine to me.
Upps, yes. Missed the missing G!
Sorry for the noise.
Andrew
next prev parent reply other threads:[~2019-05-15 16:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-15 14:46 [PATCH net-next] net: stmmac: socfpga: add RMII phy mode Dinh Nguyen
2019-05-15 15:24 ` Andrew Lunn
2019-05-15 16:18 ` Florian Fainelli
2019-05-15 16:30 ` Andrew Lunn [this message]
2019-05-15 16:18 ` Florian Fainelli
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