From: Andrew Lunn <andrew@lunn.ch>
To: Robert Hancock <hancock@sedsystems.ca>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
netdev@vger.kernel.org, Florian Fainelli <f.fainelli@gmail.com>
Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver
Date: Tue, 4 Jun 2019 18:54:52 +0200 [thread overview]
Message-ID: <20190604165452.GU19627@lunn.ch> (raw)
In-Reply-To: <7684776f-2bec-e9e2-1a79-dbc3e9844f7e@sedsystems.ca>
> So it seems like what is missing is the ability of genphy_config_init to
> detect the bits in the extended status register for 1000Base-X and add
> the corresponding mode flags. It appears bit 15 for 1000Base-X full
> duplex is standardized in 802.3 Clause 22, so I would expect Linux
> should be able to detect that and add it as a supported mode for the
> PHY. genphy_config_init is dealing with the "legacy" 32-bit mode masks
> that have no bit for 1000BaseX though.. how is that intended to work?
Hi Robert
I think you are looking at an old genphy_config_init(). The u32 has
been replaced. Adding:
#define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */
#define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BT Half */
and
if (val & ESTATUS_1000_XFULL)
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
features);
should not be a problem.
Andrew
next prev parent reply other threads:[~2019-06-04 16:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-03 23:12 [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver Robert Hancock
2019-06-03 23:27 ` Jesse Brandeburg
2019-06-04 2:39 ` Florian Fainelli
2019-06-04 5:37 ` Heiner Kallweit
2019-06-04 16:39 ` Robert Hancock
2019-06-04 16:54 ` Andrew Lunn [this message]
2019-06-04 17:37 ` Robert Hancock
2019-06-04 17:54 ` Heiner Kallweit
2019-06-04 18:12 ` Andrew Lunn
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