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Date:   Thu, 06 Jun 2019 14:03:51 -0700 (PDT)
Message-Id: <20190606.140351.938284015995890762.davem@davemloft.net>
To:     hancock@sedsystems.ca
Cc:     netdev@vger.kernel.org, anirudh@xilinx.com, John.Linn@xilinx.com,
        andrew@lunn.ch
Subject: Re: [PATCH net-next v4 00/20] Xilinx axienet driver updates (v4)
From:   David Miller <davem@davemloft.net>
In-Reply-To: <1559767353-17301-1-git-send-email-hancock@sedsystems.ca>
References: <1559767353-17301-1-git-send-email-hancock@sedsystems.ca>
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From: Robert Hancock <hancock@sedsystems.ca>
Date: Wed,  5 Jun 2019 14:42:13 -0600

> This is a series of enhancements and bug fixes in order to get the mainline
> version of this driver into a more generally usable state, including on
> x86 or ARM platforms. It also converts the driver to use the phylink API
> in order to provide support for SFP modules.
> 
> Changes since v3:
> -Added patch to document mdio child node
> -Removed goto in backward-compatibility clock rate determination code in
>  "net: axienet: Use clock framework to get device clock rate"
> -Added previous Reviewed-by: tags where patches have not been modified
>  since review

I'm going to ask for one more respin to fix up some local variable
ordering.  Otherwise looks good.

See individual patch replies.

Thanks.