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Date:   Thu, 06 Jun 2019 14:21:24 -0700 (PDT)
Message-Id: <20190606.142124.1682105557457061692.davem@davemloft.net>
To:     dinguyen@kernel.org
Cc:     netdev@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
        dalon.westergreen@intel.com
Subject: Re: [PATCH 1/2] dt-bindings: socfpga-dwmac: add
 "altr,socfpga-stmmac-a10-s10" binding
From:   David Miller <davem@davemloft.net>
In-Reply-To: <20190605150551.12791-1-dinguyen@kernel.org>
References: <20190605150551.12791-1-dinguyen@kernel.org>
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From: Dinh Nguyen <dinguyen@kernel.org>
Date: Wed,  5 Jun 2019 10:05:50 -0500

> Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10
> implementation of the stmmac ethernet controller.
> 
> On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from
> the Cyclone5 and Arria5:
>      - The emac PHY setup bits are in separate registers.
>      - The PTP reference clock select mask is different.
>      - The register to enable the emac signal from FPGA is different.
> 
> Because of these differences, the dwmac-socfpga glue logic driver will
> use this new binding to set the appropriate bits for PHY, PTP reference
> clock, and signal from FPGA.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Applied to net-next.