From: David Miller <davem@davemloft.net>
To: dinguyen@kernel.org
Cc: netdev@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
dalon.westergreen@intel.com
Subject: Re: [PATCH 2/2] net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
Date: Thu, 06 Jun 2019 14:21:30 -0700 (PDT) [thread overview]
Message-ID: <20190606.142130.1667416969493399525.davem@davemloft.net> (raw)
In-Reply-To: <20190605150551.12791-2-dinguyen@kernel.org>
From: Dinh Nguyen <dinguyen@kernel.org>
Date: Wed, 5 Jun 2019 10:05:51 -0500
> On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
> the Cyclone5 and Arria5:
> - The emac PHY setup bits are in separate registers.
> - The PTP reference clock select mask is different.
> - The register to enable the emac signal from FPGA is different.
>
> Thus, this patch creates a separate function for setting the phy modes on
> Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
> "altr,socfpga-stmmac-a10-s10".
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Applied to net-next.
next prev parent reply other threads:[~2019-06-06 21:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-05 15:05 [PATCH 1/2] dt-bindings: socfpga-dwmac: add "altr,socfpga-stmmac-a10-s10" binding Dinh Nguyen
2019-06-05 15:05 ` [PATCH 2/2] net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10 Dinh Nguyen
2019-06-06 21:21 ` David Miller [this message]
2019-06-06 21:21 ` [PATCH 1/2] dt-bindings: socfpga-dwmac: add "altr,socfpga-stmmac-a10-s10" binding David Miller
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