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To:     dinguyen@kernel.org
Cc:     netdev@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
        dalon.westergreen@intel.com
Subject: Re: [PATCH 2/2] net: stmmac: socfpga: fix phy and ptp_ref setup
 for Arria10/Stratix10
From:   David Miller <davem@davemloft.net>
In-Reply-To: <20190605150551.12791-2-dinguyen@kernel.org>
References: <20190605150551.12791-1-dinguyen@kernel.org>
        <20190605150551.12791-2-dinguyen@kernel.org>
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From: Dinh Nguyen <dinguyen@kernel.org>
Date: Wed,  5 Jun 2019 10:05:51 -0500

> On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
> the Cyclone5 and Arria5:
>  - The emac PHY setup bits are in separate registers.
>  - The PTP reference clock select mask is different.
>  - The register to enable the emac signal from FPGA is different.
> 
> Thus, this patch creates a separate function for setting the phy modes on
> Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
> "altr,socfpga-stmmac-a10-s10".
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Applied to net-next.