From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D41ACC28CC5 for ; Sat, 8 Jun 2019 11:46:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD052214AF for ; Sat, 8 Jun 2019 11:46:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994403; bh=kk/oRqzBHc+xkKfIE/IIEd6ifzx7wC2Ea6BxEhbHvmQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=0yshEPPBuz7YHP3cA95VhiKU+zwPvo9Ij/CCs5qcjAwU978ejXG9AQq1PY4R+6oYf nQQLENEjT/9i88Dqyp4pGYE0CarmGPRWCGFR7Dx5Vc2C+6l8vWEe3bKUJsKWrfiZsm ugAR1gFD3sToDRmua2mu7tD8mSacwWT+YjgHCCGg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728299AbfFHLqj (ORCPT ); Sat, 8 Jun 2019 07:46:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:59490 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727607AbfFHLmM (ORCPT ); Sat, 8 Jun 2019 07:42:12 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8A9C3214D8; Sat, 8 Jun 2019 11:42:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994132; bh=kk/oRqzBHc+xkKfIE/IIEd6ifzx7wC2Ea6BxEhbHvmQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kDK+1RbHY1AHvpAhta/n1ye0WRcsiC7BW6+pAZf1hKw1kjYMnPLHbHQ+L6xdLR+bJ /kWrMdqzQhUJeYCyMdeDsDcC8to/mT2TPErMrkXMQXngqEoxZKxontGXmtdZv/ur7p UOdMwOuSFoI3Nj+jj9H3IifT/FsgIgbhcoHiF4IE= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Max Uvarov , Heiner Kallweit , Florian Fainelli , "David S . Miller" , Sasha Levin , netdev@vger.kernel.org Subject: [PATCH AUTOSEL 5.1 62/70] net: phy: dp83867: fix speed 10 in sgmii mode Date: Sat, 8 Jun 2019 07:39:41 -0400 Message-Id: <20190608113950.8033-62-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190608113950.8033-1-sashal@kernel.org> References: <20190608113950.8033-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Max Uvarov [ Upstream commit 333061b924539c0de081339643f45514f5f1c1e6 ] For supporting 10Mps speed in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit of DP83867_10M_SGMII_CFG register has to be cleared by software. That does not affect speeds 100 and 1000 so can be done on init. Signed-off-by: Max Uvarov Cc: Heiner Kallweit Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/phy/dp83867.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 8448d01819ef..29cae4de9a4f 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -30,6 +30,8 @@ #define DP83867_STRAP_STS1 0x006E #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 +#define DP83867_10M_SGMII_CFG 0x016F +#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) #define DP83867_SW_RESET BIT(15) #define DP83867_SW_RESTART BIT(14) @@ -277,6 +279,21 @@ static int dp83867_config_init(struct phy_device *phydev) DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL); } + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* For support SPEED_10 in SGMII mode + * DP83867_10M_SGMII_RATE_ADAPT bit + * has to be cleared by software. That + * does not affect SPEED_100 and + * SPEED_1000. + */ + ret = phy_modify_mmd(phydev, DP83867_DEVADDR, + DP83867_10M_SGMII_CFG, + DP83867_10M_SGMII_RATE_ADAPT_MASK, + 0); + if (ret) + return ret; + } + /* Enable Interrupt output INT_OE in CFG3 register */ if (phy_interrupt_is_valid(phydev)) { val = phy_read(phydev, DP83867_CFG3); -- 2.20.1